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dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for R9A06G032
Add internal PCI bridge support for the R9A06G032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family, but compared to R-Car Gen2, it needs three clocks instead of one. The 'resets' property is not required for the RZ/N1 family. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Herve Codina <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Rob Herring <[email protected]>
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Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml

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@@ -15,9 +15,6 @@ description: |
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AHB. There is one bridge instance per USB port connected to the internal
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OHCI and EHCI controllers.
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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oneOf:
@@ -32,6 +29,10 @@ properties:
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- renesas,pci-r8a7793 # R-Car M2-N
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- renesas,pci-r8a7794 # R-Car E2
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- const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
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- items:
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- enum:
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- renesas,pci-r9a06g032 # RZ/N1D
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- const: renesas,pci-rzn1 # RZ/N1
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reg:
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items:
@@ -41,13 +42,9 @@ properties:
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Device clock
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clocks: true
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clock-names:
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items:
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- const: pclk
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clock-names: true
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resets:
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maxItems: 1
@@ -106,13 +103,46 @@ required:
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- interrupt-map
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- interrupt-map-mask
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- clocks
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- resets
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- power-domains
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- bus-range
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- "#address-cells"
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- "#size-cells"
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- "#interrupt-cells"
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,pci-rzn1
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then:
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properties:
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clocks:
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items:
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- description: Internal bus clock (AHB) for HOST
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- description: Internal bus clock (AHB) Power Management
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- description: PCI clock for USB subsystem
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clock-names:
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items:
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- const: hclkh
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- const: hclkpm
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- const: pciclk
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required:
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- clock-names
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else:
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properties:
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clocks:
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items:
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- description: Device clock
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clock-names:
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items:
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- const: pclk
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required:
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- resets
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unevaluatedProperties: false
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examples:

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