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Andrey Grodzovskyalexdeucher
Andrey Grodzovsky
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alexdeucher
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drm/amdgpu: Add mem_sync implementation for all the ASICs.
Implement the .mem_sync hook defined earlier. v2: Rename functions Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8020,6 +8020,29 @@ static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
80208020
return 0;
80218021
}
80228022

8023+
static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8024+
{
8025+
const unsigned int gcr_cntl =
8026+
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8027+
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8028+
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8029+
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8030+
PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8031+
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8032+
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8033+
PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8034+
8035+
/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8036+
amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8037+
amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8038+
amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
8039+
amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
8040+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8041+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
8042+
amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8043+
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8044+
}
8045+
80238046
static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
80248047
.name = "gfx_v10_0",
80258048
.early_init = gfx_v10_0_early_init,
@@ -8067,7 +8090,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
80678090
3 + /* CNTX_CTRL */
80688091
5 + /* HDP_INVL */
80698092
8 + 8 + /* FENCE x2 */
8070-
2, /* SWITCH_BUFFER */
8093+
2 + /* SWITCH_BUFFER */
8094+
8, /* gfx_v10_0_emit_mem_sync */
80718095
.emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
80728096
.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
80738097
.emit_fence = gfx_v10_0_ring_emit_fence,
@@ -8089,6 +8113,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
80898113
.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
80908114
.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
80918115
.soft_recovery = gfx_v10_0_ring_soft_recovery,
8116+
.emit_mem_sync = gfx_v10_0_emit_mem_sync,
80928117
};
80938118

80948119
static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3465,6 +3465,18 @@ static int gfx_v6_0_set_powergating_state(void *handle,
34653465
return 0;
34663466
}
34673467

3468+
static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring)
3469+
{
3470+
amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3471+
amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3472+
PACKET3_TC_ACTION_ENA |
3473+
PACKET3_SH_KCACHE_ACTION_ENA |
3474+
PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */
3475+
amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
3476+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
3477+
amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
3478+
}
3479+
34683480
static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
34693481
.name = "gfx_v6_0",
34703482
.early_init = gfx_v6_0_early_init,
@@ -3495,7 +3507,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
34953507
14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
34963508
7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
34973509
SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3498-
3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3510+
3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3511+
5, /* SURFACE_SYNC */
34993512
.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
35003513
.emit_ib = gfx_v6_0_ring_emit_ib,
35013514
.emit_fence = gfx_v6_0_ring_emit_fence,
@@ -3506,6 +3519,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
35063519
.insert_nop = amdgpu_ring_insert_nop,
35073520
.emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
35083521
.emit_wreg = gfx_v6_0_ring_emit_wreg,
3522+
.emit_mem_sync = gfx_v6_0_emit_mem_sync,
35093523
};
35103524

35113525
static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4998,6 +4998,18 @@ static int gfx_v7_0_set_powergating_state(void *handle,
49984998
return 0;
49994999
}
50005000

5001+
static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring)
5002+
{
5003+
amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
5004+
amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
5005+
PACKET3_TC_ACTION_ENA |
5006+
PACKET3_SH_KCACHE_ACTION_ENA |
5007+
PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */
5008+
amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
5009+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
5010+
amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
5011+
}
5012+
50015013
static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
50025014
.name = "gfx_v7_0",
50035015
.early_init = gfx_v7_0_early_init,
@@ -5030,7 +5042,8 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
50305042
12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
50315043
7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
50325044
CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5033-
3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5045+
3 + 4 + /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5046+
5, /* SURFACE_SYNC */
50345047
.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
50355048
.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
50365049
.emit_fence = gfx_v7_0_ring_emit_fence_gfx,
@@ -5045,6 +5058,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
50455058
.emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
50465059
.emit_wreg = gfx_v7_0_ring_emit_wreg,
50475060
.soft_recovery = gfx_v7_0_ring_soft_recovery,
5061+
.emit_mem_sync = gfx_v7_0_emit_mem_sync,
50485062
};
50495063

50505064
static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6817,6 +6817,19 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
68176817
return 0;
68186818
}
68196819

6820+
static void gfx_v8_0_emit_mem_sync(struct amdgpu_ring *ring)
6821+
{
6822+
amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
6823+
amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6824+
PACKET3_TC_ACTION_ENA |
6825+
PACKET3_SH_KCACHE_ACTION_ENA |
6826+
PACKET3_SH_ICACHE_ACTION_ENA |
6827+
PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6828+
amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6829+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6830+
amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6831+
}
6832+
68206833
static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
68216834
.name = "gfx_v8_0",
68226835
.early_init = gfx_v8_0_early_init,
@@ -6863,7 +6876,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
68636876
3 + /* CNTX_CTRL */
68646877
5 + /* HDP_INVL */
68656878
12 + 12 + /* FENCE x2 */
6866-
2, /* SWITCH_BUFFER */
6879+
2 + /* SWITCH_BUFFER */
6880+
5, /* SURFACE_SYNC */
68676881
.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
68686882
.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
68696883
.emit_fence = gfx_v8_0_ring_emit_fence_gfx,
@@ -6881,6 +6895,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
68816895
.patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
68826896
.emit_wreg = gfx_v8_0_ring_emit_wreg,
68836897
.soft_recovery = gfx_v8_0_ring_soft_recovery,
6898+
.emit_mem_sync = gfx_v8_0_emit_mem_sync,
68846899
};
68856900

68866901
static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6634,6 +6634,25 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
66346634
return 0;
66356635
}
66366636

6637+
static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
6638+
{
6639+
const unsigned int cp_coher_cntl =
6640+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
6641+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
6642+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
6643+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
6644+
PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
6645+
6646+
/* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
6647+
amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
6648+
amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
6649+
amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6650+
amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
6651+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6652+
amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
6653+
amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6654+
}
6655+
66376656
static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
66386657
.name = "gfx_v9_0",
66396658
.early_init = gfx_v9_0_early_init,
@@ -6680,7 +6699,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
66806699
3 + /* CNTX_CTRL */
66816700
5 + /* HDP_INVL */
66826701
8 + 8 + /* FENCE x2 */
6683-
2, /* SWITCH_BUFFER */
6702+
2 + /* SWITCH_BUFFER */
6703+
7, /* gfx_v9_0_emit_mem_sync */
66846704
.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
66856705
.emit_ib = gfx_v9_0_ring_emit_ib_gfx,
66866706
.emit_fence = gfx_v9_0_ring_emit_fence,
@@ -6701,6 +6721,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
67016721
.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
67026722
.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
67036723
.soft_recovery = gfx_v9_0_ring_soft_recovery,
6724+
.emit_mem_sync = gfx_v9_0_emit_mem_sync,
67046725
};
67056726

67066727
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {

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