Skip to content

Commit 302b84e

Browse files
committed
Revert "PCI: Mark LSI FW643 to avoid bus reset"
This reverts commit 29a43dc. 29a43dc ("PCI: Mark LSI FW643 to avoid bus reset") by Edmund was based on the assumption that the LSI / Agere FW643 has a defect such that it can't recover after a Secondary Bus Reset (SBR). But Takashi Sakamoto reported that SBR works fine on this same FW643 device in an AMD Ryzen 5 2400G system, so apparently there is some other aspect of Edmund's system that accounts for the issue. The down side of 29a43dc is that when the FW643 is assigned to a VM, avoiding the SBR means we leak data out of the VM. Revert 29a43dc until we figure out a better solution. In the meantime, we can use the sysfs "reset_method" interface to restrict the available reset methods. Link: https://lore.kernel.org/r/[email protected] Fixes: 29a43dc ("PCI: Mark LSI FW643 to avoid bus reset") Reported-by: Takashi Sakamoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Takashi Sakamoto <[email protected]>
1 parent 3cf5abf commit 302b84e

File tree

1 file changed

+0
-8
lines changed

1 file changed

+0
-8
lines changed

drivers/pci/quirks.c

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3765,14 +3765,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
37653765
*/
37663766
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
37673767

3768-
/*
3769-
* Apparently the LSI / Agere FW643 can't recover after a Secondary Bus
3770-
* Reset and requires a power-off or suspend/resume and rescan. Prevent
3771-
* use of that reset.
3772-
*/
3773-
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATT, 0x5900, quirk_no_bus_reset);
3774-
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATT, 0x5901, quirk_no_bus_reset);
3775-
37763768
/*
37773769
* Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
37783770
* automatically disables LTSSM when Secondary Bus Reset is received and

0 commit comments

Comments
 (0)