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Merge tag 'arc-5.6-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta: - Fix __ALIGN_STR and __ALIGN to not use default junk padding - Misc Kconfig cleanups, header updates * tag 'arc-5.6-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: define __ALIGN_STR and __ALIGN symbols for ARC ARC: show_regs: reduce lines of output ARC: Replace <linux/clk-provider.h> by <linux/of_clk.h> ARC: fpu: fix randconfig build error reported by 0-day test service ARC: fix some Kconfig typos ARC: Cleanup old Kconfig IO scheduler options
2 parents 6693075 + 8d92e99 commit 3086ae0

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9 files changed

+19
-26
lines changed

9 files changed

+19
-26
lines changed

arch/arc/Kconfig

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@ config ARC_CPU_HS
154154
help
155155
Support for ARC HS38x Cores based on ARCv2 ISA
156156
The notable features are:
157-
- SMP configurations of upto 4 core with coherency
157+
- SMP configurations of up to 4 cores with coherency
158158
- Optional L2 Cache and IO-Coherency
159159
- Revised Interrupt Architecture (multiple priorites, reg banks,
160160
auto stack switch, auto regfile save/restore)
@@ -192,7 +192,7 @@ config ARC_SMP_HALT_ON_RESET
192192
help
193193
In SMP configuration cores can be configured as Halt-on-reset
194194
or they could all start at same time. For Halt-on-reset, non
195-
masters are parked until Master kicks them so they can start of
195+
masters are parked until Master kicks them so they can start off
196196
at designated entry point. For other case, all jump to common
197197
entry point and spin wait for Master's signal.
198198

arch/arc/configs/nps_defconfig

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,6 @@ CONFIG_MODULES=y
2121
CONFIG_MODULE_FORCE_LOAD=y
2222
CONFIG_MODULE_UNLOAD=y
2323
# CONFIG_BLK_DEV_BSG is not set
24-
# CONFIG_IOSCHED_DEADLINE is not set
25-
# CONFIG_IOSCHED_CFQ is not set
2624
CONFIG_ARC_PLAT_EZNPS=y
2725
CONFIG_SMP=y
2826
CONFIG_NR_CPUS=4096

arch/arc/configs/nsimosci_defconfig

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,6 @@ CONFIG_ISA_ARCOMPACT=y
2020
CONFIG_KPROBES=y
2121
CONFIG_MODULES=y
2222
# CONFIG_BLK_DEV_BSG is not set
23-
# CONFIG_IOSCHED_DEADLINE is not set
24-
# CONFIG_IOSCHED_CFQ is not set
2523
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci"
2624
# CONFIG_COMPACTION is not set
2725
CONFIG_NET=y

arch/arc/configs/nsimosci_hs_defconfig

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,6 @@ CONFIG_PERF_EVENTS=y
1919
CONFIG_KPROBES=y
2020
CONFIG_MODULES=y
2121
# CONFIG_BLK_DEV_BSG is not set
22-
# CONFIG_IOSCHED_DEADLINE is not set
23-
# CONFIG_IOSCHED_CFQ is not set
2422
CONFIG_ISA_ARCV2=y
2523
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs"
2624
# CONFIG_COMPACTION is not set

arch/arc/configs/nsimosci_hs_smp_defconfig

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,6 @@ CONFIG_PERF_EVENTS=y
1414
CONFIG_KPROBES=y
1515
CONFIG_MODULES=y
1616
# CONFIG_BLK_DEV_BSG is not set
17-
# CONFIG_IOSCHED_DEADLINE is not set
18-
# CONFIG_IOSCHED_CFQ is not set
1917
CONFIG_ISA_ARCV2=y
2018
CONFIG_SMP=y
2119
# CONFIG_ARC_TIMERS_64BIT is not set

arch/arc/include/asm/fpu.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,8 @@ extern void fpu_init_task(struct pt_regs *regs);
4343

4444
#endif /* !CONFIG_ISA_ARCOMPACT */
4545

46+
struct task_struct;
47+
4648
extern void fpu_save_restore(struct task_struct *p, struct task_struct *n);
4749

4850
#else /* !CONFIG_ARC_FPU_SAVE_RESTORE */

arch/arc/include/asm/linkage.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,8 @@
2929
.endm
3030

3131
#define ASM_NL ` /* use '`' to mark new line in macro */
32+
#define __ALIGN .align 4
33+
#define __ALIGN_STR __stringify(__ALIGN)
3234

3335
/* annotation for data we want in DCCM - if enabled in .config */
3436
.macro ARCFP_DATA nm

arch/arc/kernel/setup.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,11 @@
88
#include <linux/delay.h>
99
#include <linux/root_dev.h>
1010
#include <linux/clk.h>
11-
#include <linux/clk-provider.h>
1211
#include <linux/clocksource.h>
1312
#include <linux/console.h>
1413
#include <linux/module.h>
1514
#include <linux/cpu.h>
15+
#include <linux/of_clk.h>
1616
#include <linux/of_fdt.h>
1717
#include <linux/of.h>
1818
#include <linux/cache.h>

arch/arc/kernel/troubleshoot.c

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -104,8 +104,7 @@ static void show_faulting_vma(unsigned long address)
104104
if (IS_ERR(nm))
105105
nm = "?";
106106
}
107-
pr_info(" @off 0x%lx in [%s]\n"
108-
" VMA: 0x%08lx to 0x%08lx\n",
107+
pr_info(" @off 0x%lx in [%s] VMA: 0x%08lx to 0x%08lx\n",
109108
vma->vm_start < TASK_UNMAPPED_BASE ?
110109
address : address - vma->vm_start,
111110
nm, vma->vm_start, vma->vm_end);
@@ -120,8 +119,6 @@ static void show_ecr_verbose(struct pt_regs *regs)
120119
unsigned int vec, cause_code;
121120
unsigned long address;
122121

123-
pr_info("\n[ECR ]: 0x%08lx => ", regs->event);
124-
125122
/* For Data fault, this is data address not instruction addr */
126123
address = current->thread.fault_address;
127124

@@ -130,10 +127,10 @@ static void show_ecr_verbose(struct pt_regs *regs)
130127

131128
/* For DTLB Miss or ProtV, display the memory involved too */
132129
if (vec == ECR_V_DTLB_MISS) {
133-
pr_cont("Invalid %s @ 0x%08lx by insn @ 0x%08lx\n",
130+
pr_cont("Invalid %s @ 0x%08lx by insn @ %pS\n",
134131
(cause_code == 0x01) ? "Read" :
135132
((cause_code == 0x02) ? "Write" : "EX"),
136-
address, regs->ret);
133+
address, (void *)regs->ret);
137134
} else if (vec == ECR_V_ITLB_MISS) {
138135
pr_cont("Insn could not be fetched\n");
139136
} else if (vec == ECR_V_MACH_CHK) {
@@ -191,31 +188,31 @@ void show_regs(struct pt_regs *regs)
191188

192189
show_ecr_verbose(regs);
193190

194-
pr_info("[EFA ]: 0x%08lx\n[BLINK ]: %pS\n[ERET ]: %pS\n",
195-
current->thread.fault_address,
196-
(void *)regs->blink, (void *)regs->ret);
197-
198191
if (user_mode(regs))
199192
show_faulting_vma(regs->ret); /* faulting code, not data */
200193

201-
pr_info("[STAT32]: 0x%08lx", regs->status32);
194+
pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\n",
195+
regs->event, current->thread.fault_address, regs->ret);
196+
197+
pr_info("STAT32: 0x%08lx", regs->status32);
202198

203199
#define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : ""
204200

205201
#ifdef CONFIG_ISA_ARCOMPACT
206-
pr_cont(" : %2s%2s%2s%2s%2s%2s%2s\n",
202+
pr_cont(" [%2s%2s%2s%2s%2s%2s%2s]",
207203
(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
208204
STS_BIT(regs, DE), STS_BIT(regs, AE),
209205
STS_BIT(regs, A2), STS_BIT(regs, A1),
210206
STS_BIT(regs, E2), STS_BIT(regs, E1));
211207
#else
212-
pr_cont(" : %2s%2s%2s%2s\n",
208+
pr_cont(" [%2s%2s%2s%2s]",
213209
STS_BIT(regs, IE),
214210
(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
215211
STS_BIT(regs, DE), STS_BIT(regs, AE));
216212
#endif
217-
pr_info("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n",
218-
regs->bta, regs->sp, regs->fp);
213+
pr_cont(" BTA: 0x%08lx\n", regs->bta);
214+
pr_info("BLK: %pS\n SP: 0x%08lx FP: 0x%08lx\n",
215+
(void *)regs->blink, regs->sp, regs->fp);
219216
pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
220217
regs->lp_start, regs->lp_end, regs->lp_count);
221218

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