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Merge tag 'dmaengine-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul: "New support / Core: - Remove DMA_MEMCPY_SG for lack of users - Tegra 234 dmaengine support - Mediatek MT8365 dma support - Apple ADMAC driver Updates: - Yaml conversion for ST-Ericsson DMA40 binding and Freescale edma - rz-dmac updates and device_synchronize support - Bunch of typo in comments fixes in drivers - multithread support in sf-pdma driver" * tag 'dmaengine-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (50 commits) dmaengine: mediatek: mtk-hsdma: Fix typo 'the the' in comment dmaengine: axi-dmac: check cache coherency register dmaengine: sh: rz-dmac: Add device_synchronize callback dmaengine: sprd: Cleanup in .remove() after pm_runtime_get_sync() failed dmaengine: tegra: Add terminate() for Tegra234 dt-bindings: dmaengine: Add compatible for Tegra234 dmaengine: xilinx: use strscpy to replace strlcpy dmaengine: imx-sdma: Add FIFO stride support for multi FIFO script dmaengine: idxd: Correct IAX operation code names dmaengine: imx-dma: Cast of_device_get_match_data() with (uintptr_t) dmaengine: dw-axi-dmac: ignore interrupt if no descriptor dmaengine: dw-axi-dmac: do not print NULL LLI during error dmaengine: altera-msgdma: Fixed some inconsistent function name descriptions dmaengine: imx-sdma: Add missing struct documentation dmaengine: sf-pdma: Add multithread support for a DMA channel dt-bindings: dma: dw-axi-dmac: extend the number of interrupts dmaengine: dmatest: use strscpy to replace strlcpy dmaengine: ste_dma40: fix typo in comment dmaengine: jz4780: fix typo in comment dmaengine: s3c24xx: fix typo in comment ...
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‎Documentation/devicetree/bindings/dma/apple,admac.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/apple,admac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Apple Audio DMA Controller (ADMAC)
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description: |
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Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples
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on SoCs from the "Apple Silicon" family.
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The controller has been seen with up to 24 channels. Even-numbered channels
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are TX-only, odd-numbered are RX-only. Individual channels are coupled to
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fixed device endpoints.
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maintainers:
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- Martin Povišer <[email protected]>
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allOf:
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- $ref: "dma-controller.yaml#"
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properties:
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compatible:
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items:
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- enum:
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- apple,t6000-admac
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- apple,t8103-admac
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- const: apple,admac
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reg:
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maxItems: 1
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'#dma-cells':
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const: 1
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description:
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Clients specify a single cell with channel number.
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dma-channels:
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maximum: 24
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interrupts:
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minItems: 4
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maxItems: 4
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description:
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Interrupts that correspond to the 4 IRQ outputs of the controller. Usually
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only one of the controller outputs will be connected as an usable interrupt
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source. The remaining interrupts will be left without a valid value, e.g.
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in an interrupts-extended list the disconnected positions will contain
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an empty phandle reference <0>.
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required:
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- compatible
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- reg
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- '#dma-cells'
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- dma-channels
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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aic: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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admac: dma-controller@238200000 {
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compatible = "apple,t8103-admac", "apple,admac";
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reg = <0x38200000 0x34000>;
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dma-channels = <24>;
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interrupts-extended = <0>,
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<&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>,
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<0>,
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<0>;
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#dma-cells = <1>;
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};

‎Documentation/devicetree/bindings/dma/fsl,edma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale enhanced Direct Memory Access(eDMA) Controller
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description: |
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The eDMA channels have multiplex capability by programmable
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memory-mapped registers. channels are split into two groups, called
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DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
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by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.
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maintainers:
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- Peng Fan <[email protected]>
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,vf610-edma
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- fsl,imx7ulp-edma
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- items:
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- const: fsl,ls1028a-edma
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- const: fsl,vf610-edma
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reg:
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minItems: 2
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maxItems: 3
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interrupts:
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minItems: 2
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maxItems: 17
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interrupt-names:
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minItems: 2
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maxItems: 17
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"#dma-cells":
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const: 2
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dma-channels:
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const: 32
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clocks:
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maxItems: 2
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clock-names:
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maxItems: 2
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big-endian:
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description: |
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If present registers and hardware scatter/gather descriptors of the
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eDMA are implemented in big endian mode, otherwise in little mode.
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type: boolean
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required:
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- "#dma-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- dma-channels
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allOf:
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- $ref: "dma-controller.yaml#"
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- if:
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properties:
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compatible:
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contains:
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const: fsl,vf610-edma
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then:
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properties:
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clock-names:
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items:
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- const: dmamux0
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- const: dmamux1
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interrupts:
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maxItems: 2
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interrupt-names:
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items:
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- const: edma-tx
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- const: edma-err
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reg:
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maxItems: 3
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx7ulp-edma
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then:
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properties:
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clock-names:
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items:
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- const: dma
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- const: dmamux0
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interrupts:
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maxItems: 17
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reg:
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maxItems: 2
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/vf610-clock.h>
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edma0: dma-controller@40018000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x40018000 0x2000>,
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<0x40024000 0x1000>,
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<0x40025000 0x1000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/imx7ulp-clock.h>
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edma1: dma-controller@40080000 {
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#dma-cells = <2>;
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compatible = "fsl,imx7ulp-edma";
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reg = <0x40080000 0x2000>,
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<0x40210000 0x1000>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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/* last is eDMA2-ERR interrupt */
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dma", "dmamux0";
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clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
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};

‎Documentation/devicetree/bindings/dma/fsl-edma.txt

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‎Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml

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- items:
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- enum:
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- mediatek,mt2712-uart-dma
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- mediatek,mt8365-uart-dma
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- mediatek,mt8516-uart-dma
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- const: mediatek,mt6577-uart-dma
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- enum:

‎Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml

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oneOf:
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- const: nvidia,tegra186-gpcdma
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- items:
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- const: nvidia,tegra194-gpcdma
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- enum:
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- nvidia,tegra234-gpcdma
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- nvidia,tegra194-gpcdma
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- const: nvidia,tegra186-gpcdma
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"#dma-cells":

‎Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml

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- const: axidma_apb_regs
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interrupts:
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maxItems: 1
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description:
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If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this
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will be per-channel interrupts. Otherwise, this is a single combined IRQ
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for all channels.
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minItems: 1
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maxItems: 8
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clocks:
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items:

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