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Merge branches 'for-next/cpufeature', 'for-next/misc', 'for-next/kselftest', 'for-next/mte', 'for-next/errata', 'for-next/acpi', 'for-next/gic-v3-pmr' and 'for-next/doc', remote-tracking branch 'arm64/for-next/perf' into for-next/core
* arm64/for-next/perf: perf: add missing MODULE_DESCRIPTION() macros perf: arm_pmuv3: Include asm/arm_pmuv3.h from linux/perf/arm_pmuv3.h perf: arm_v6/7_pmu: Drop non-DT probe support perf/arm: Move 32-bit PMU drivers to drivers/perf/ perf: arm_pmuv3: Drop unnecessary IS_ENABLED(CONFIG_ARM64) check perf: arm_pmuv3: Avoid assigning fixed cycle counter with threshold perf: imx_perf: add support for i.MX95 platform perf: imx_perf: fix counter start and config sequence perf: imx_perf: refactor driver for imx93 perf: imx_perf: let the driver manage the counter usage rather the user perf: imx_perf: add macro definitions for parsing config attr dt-bindings: perf: fsl-imx-ddr: Add i.MX95 compatible perf: pmuv3: Add new Cortex and Neoverse PMUs dt-bindings: arm: pmu: Add new Cortex and Neoverse cores perf/arm-cmn: Enable support for tertiary match group perf/arm-cmn: Decouple wp_config registers from filter group number * for-next/cpufeature: : Various cpufeature infrastructure patches arm64/cpufeature: Replace custom macros with fields from ID_AA64PFR0_EL1 KVM: arm64: Replace custom macros with fields from ID_AA64PFR0_EL1 arm64/cpufeatures/kvm: Add ARMv8.9 FEAT_ECBHB bits in ID_AA64MMFR1 register * for-next/misc: : Miscellaneous patches arm64: smp: Fix missing IPI statistics arm64: Cleanup __cpu_set_tcr_t0sz() arm64/mm: Stop using ESR_ELx_FSC_TYPE during fault arm64: Kconfig: fix typo in __builtin_return_adddress ARM64: reloc_test: add missing MODULE_DESCRIPTION() macro arm64: implement raw_smp_processor_id() using thread_info arm64/arch_timer: include <linux/percpu.h> * for-next/kselftest: : arm64 kselftest updates selftests: arm64: tags: remove the result script selftests: arm64: tags_test: conform test to TAP output kselftest/arm64: Fix a couple of spelling mistakes kselftest/arm64: Fix redundancy of a testcase kselftest/arm64: Include kernel mode NEON in fp-stress * for-next/mte: : MTE updates arm64: mte: Make mte_check_tfsr_*() conditional on KASAN instead of MTE * for-next/errata: : Arm CPU errata workarounds arm64: errata: Expand speculative SSBS workaround arm64: errata: Unify speculative SSBS errata logic arm64: cputype: Add Cortex-X925 definitions arm64: cputype: Add Cortex-A720 definitions arm64: cputype: Add Cortex-X3 definitions * for-next/acpi: : arm64 ACPI patches ACPI: Add acpi=nospcr to disable ACPI SPCR as default console on ARM64 ACPI / amba: Drop unnecessary check for registered amba_dummy_clk arm64: FFH: Move ACPI specific code into drivers/acpi/arm64/ arm64: cpuidle: Move ACPI specific code into drivers/acpi/arm64/ ACPI: arm64: Sort entries alphabetically * for-next/gic-v3-pmr: : arm64: irqchip/gic-v3: Use compiletime constant PMR values arm64: irqchip/gic-v3: Select priorities at boot time irqchip/gic-v3: Detect GICD_CTRL.DS and SCR_EL3.FIQ earlier irqchip/gic-v3: Make distributor priorities variables irqchip/gic-common: Remove sync_access callback wordpart.h: Add REPEAT_BYTE_U32() * for-next/doc: : arm64 documentation updates Documentation: arm64: Update memory.rst for TBI
9 parents 42bebc7 + 056600f + 916b93f + 6e3bc73 + 26ca442 + 75b3c43 + f5a4af3 + 18fdb63 + 5e30c16 commit 3346c56

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‎Documentation/admin-guide/kernel-parameters.txt

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
acpi= [HW,ACPI,X86,ARM64,RISCV64,EARLY]
1313
Advanced Configuration and Power Interface
1414
Format: { force | on | off | strict | noirq | rsdt |
15-
copy_dsdt }
15+
copy_dsdt | nospcr }
1616
force -- enable ACPI if default was off
1717
on -- enable ACPI but allow fallback to DT [arm64,riscv64]
1818
off -- disable ACPI if default was on
@@ -21,8 +21,12 @@
2121
strictly ACPI specification compliant.
2222
rsdt -- prefer RSDT over (default) XSDT
2323
copy_dsdt -- copy DSDT to memory
24-
For ARM64 and RISCV64, ONLY "acpi=off", "acpi=on" or
25-
"acpi=force" are available
24+
nospcr -- disable console in ACPI SPCR table as
25+
default _serial_ console on ARM64
26+
For ARM64, ONLY "acpi=off", "acpi=on", "acpi=force" or
27+
"acpi=nospcr" are available
28+
For RISCV64, ONLY "acpi=off", "acpi=on" or "acpi=force"
29+
are available
2630

2731
See also Documentation/power/runtime_pm.rst, pci=noacpi
2832

‎Documentation/arch/arm64/memory.rst

Lines changed: 20 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -18,12 +18,10 @@ ARMv8.2 adds optional support for Large Virtual Address space. This is
1818
only available when running with a 64KB page size and expands the
1919
number of descriptors in the first level of translation.
2020

21-
User addresses have bits 63:48 set to 0 while the kernel addresses have
22-
the same bits set to 1. TTBRx selection is given by bit 63 of the
23-
virtual address. The swapper_pg_dir contains only kernel (global)
24-
mappings while the user pgd contains only user (non-global) mappings.
25-
The swapper_pg_dir address is written to TTBR1 and never written to
26-
TTBR0.
21+
TTBRx selection is given by bit 55 of the virtual address. The
22+
swapper_pg_dir contains only kernel (global) mappings while the user pgd
23+
contains only user (non-global) mappings. The swapper_pg_dir address is
24+
written to TTBR1 and never written to TTBR0.
2725

2826

2927
AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
@@ -65,29 +63,29 @@ Translation table lookup with 4KB pages::
6563
+--------+--------+--------+--------+--------+--------+--------+--------+
6664
|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
6765
+--------+--------+--------+--------+--------+--------+--------+--------+
68-
| | | | | |
69-
| | | | | v
70-
| | | | | [11:0] in-page offset
71-
| | | | +-> [20:12] L3 index
72-
| | | +-----------> [29:21] L2 index
73-
| | +---------------------> [38:30] L1 index
74-
| +-------------------------------> [47:39] L0 index
75-
+-------------------------------------------------> [63] TTBR0/1
66+
| | | | | |
67+
| | | | | v
68+
| | | | | [11:0] in-page offset
69+
| | | | +-> [20:12] L3 index
70+
| | | +-----------> [29:21] L2 index
71+
| | +---------------------> [38:30] L1 index
72+
| +-------------------------------> [47:39] L0 index
73+
+----------------------------------------> [55] TTBR0/1
7674

7775

7876
Translation table lookup with 64KB pages::
7977

8078
+--------+--------+--------+--------+--------+--------+--------+--------+
8179
|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
8280
+--------+--------+--------+--------+--------+--------+--------+--------+
83-
| | | | |
84-
| | | | v
85-
| | | | [15:0] in-page offset
86-
| | | +----------> [28:16] L3 index
87-
| | +--------------------------> [41:29] L2 index
88-
| +-------------------------------> [47:42] L1 index (48-bit)
89-
| [51:42] L1 index (52-bit)
90-
+-------------------------------------------------> [63] TTBR0/1
81+
| | | | |
82+
| | | | v
83+
| | | | [15:0] in-page offset
84+
| | | +----------> [28:16] L3 index
85+
| | +--------------------------> [41:29] L2 index
86+
| +-------------------------------> [47:42] L1 index (48-bit)
87+
| [51:42] L1 index (52-bit)
88+
+----------------------------------------> [55] TTBR0/1
9189

9290

9391
When using KVM without the Virtualization Host Extensions, the

‎Documentation/arch/arm64/silicon-errata.rst

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -132,16 +132,26 @@ stable kernels.
132132
+----------------+-----------------+-----------------+-----------------------------+
133133
| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
134134
+----------------+-----------------+-----------------+-----------------------------+
135+
| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 |
136+
+----------------+-----------------+-----------------+-----------------------------+
135137
| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 |
136138
+----------------+-----------------+-----------------+-----------------------------+
139+
| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
140+
+----------------+-----------------+-----------------+-----------------------------+
137141
| ARM | Cortex-X1 | #1502854 | N/A |
138142
+----------------+-----------------+-----------------+-----------------------------+
139143
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
140144
+----------------+-----------------+-----------------+-----------------------------+
141145
| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
142146
+----------------+-----------------+-----------------+-----------------------------+
147+
| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 |
148+
+----------------+-----------------+-----------------+-----------------------------+
149+
| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 |
150+
+----------------+-----------------+-----------------+-----------------------------+
143151
| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 |
144152
+----------------+-----------------+-----------------+-----------------------------+
153+
| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 |
154+
+----------------+-----------------+-----------------+-----------------------------+
145155
| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
146156
+----------------+-----------------+-----------------+-----------------------------+
147157
| ARM | Neoverse-N1 | #1349291 | N/A |
@@ -156,9 +166,13 @@ stable kernels.
156166
+----------------+-----------------+-----------------+-----------------------------+
157167
| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 |
158168
+----------------+-----------------+-----------------+-----------------------------+
169+
| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 |
170+
+----------------+-----------------+-----------------+-----------------------------+
159171
| ARM | Neoverse-V1 | #1619801 | N/A |
160172
+----------------+-----------------+-----------------+-----------------------------+
161-
| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 |
173+
| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
174+
+----------------+-----------------+-----------------+-----------------------------+
175+
| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
162176
+----------------+-----------------+-----------------+-----------------------------+
163177
| ARM | MMU-500 | #841119,826419 | N/A |
164178
+----------------+-----------------+-----------------+-----------------------------+

‎arch/arm64/Kconfig

Lines changed: 12 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -381,7 +381,7 @@ config BROKEN_GAS_INST
381381

382382
config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
383383
bool
384-
# Clang's __builtin_return_adddress() strips the PAC since 12.0.0
384+
# Clang's __builtin_return_address() strips the PAC since 12.0.0
385385
# https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
386386
default y if CC_IS_CLANG
387387
# GCC's __builtin_return_address() strips the PAC since 11.1.0,
@@ -1067,34 +1067,21 @@ config ARM64_ERRATUM_3117295
10671067

10681068
If unsure, say Y.
10691069

1070-
config ARM64_WORKAROUND_SPECULATIVE_SSBS
1071-
bool
1072-
10731070
config ARM64_ERRATUM_3194386
1074-
bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing"
1075-
select ARM64_WORKAROUND_SPECULATIVE_SSBS
1071+
bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"
10761072
default y
10771073
help
1078-
This option adds the workaround for ARM Cortex-X4 erratum 3194386.
1074+
This option adds the workaround for the following errata:
10791075

1080-
On affected cores "MSR SSBS, #0" instructions may not affect
1081-
subsequent speculative instructions, which may permit unexepected
1082-
speculative store bypassing.
1083-
1084-
Work around this problem by placing a speculation barrier after
1085-
kernel changes to SSBS. The presence of the SSBS special-purpose
1086-
register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such
1087-
that userspace will use the PR_SPEC_STORE_BYPASS prctl to change
1088-
SSBS.
1089-
1090-
If unsure, say Y.
1091-
1092-
config ARM64_ERRATUM_3312417
1093-
bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing"
1094-
select ARM64_WORKAROUND_SPECULATIVE_SSBS
1095-
default y
1096-
help
1097-
This option adds the workaround for ARM Neoverse-V3 erratum 3312417.
1076+
* ARM Cortex-A710 erratam 3324338
1077+
* ARM Cortex-A720 erratum 3456091
1078+
* ARM Cortex-X2 erratum 3324338
1079+
* ARM Cortex-X3 erratum 3324335
1080+
* ARM Cortex-X4 erratum 3194386
1081+
* ARM Cortex-X925 erratum 3324334
1082+
* ARM Neoverse N2 erratum 3324339
1083+
* ARM Neoverse V2 erratum 3324336
1084+
* ARM Neoverse-V3 erratum 3312417
10981085

10991086
On affected cores "MSR SSBS, #0" instructions may not affect
11001087
subsequent speculative instructions, which may permit unexepected
@@ -1108,7 +1095,6 @@ config ARM64_ERRATUM_3312417
11081095

11091096
If unsure, say Y.
11101097

1111-
11121098
config CAVIUM_ERRATUM_22375
11131099
bool "Cavium erratum 22375, 24313"
11141100
default y

‎arch/arm64/include/asm/arch_gicv3.h

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -175,21 +175,6 @@ static inline bool gic_prio_masking_enabled(void)
175175

176176
static inline void gic_pmr_mask_irqs(void)
177177
{
178-
BUILD_BUG_ON(GICD_INT_DEF_PRI < (__GIC_PRIO_IRQOFF |
179-
GIC_PRIO_PSR_I_SET));
180-
BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
181-
/*
182-
* Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
183-
* and non-secure PMR accesses are not subject to the shifts that
184-
* are applied to IRQ priorities
185-
*/
186-
BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
187-
/*
188-
* Same situation as above, but now we make sure that we can mask
189-
* regular interrupts.
190-
*/
191-
BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) < (__GIC_PRIO_IRQOFF_NS |
192-
GIC_PRIO_PSR_I_SET));
193178
gic_write_pmr(GIC_PRIO_IRQOFF);
194179
}
195180

‎arch/arm64/include/asm/arch_timer.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
#include <linux/bug.h>
1616
#include <linux/init.h>
1717
#include <linux/jump_label.h>
18-
#include <linux/smp.h>
18+
#include <linux/percpu.h>
1919
#include <linux/types.h>
2020

2121
#include <clocksource/arm_arch_timer.h>

‎arch/arm64/include/asm/cpucaps.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ cpucap_is_possible(const unsigned int cap)
5959
case ARM64_WORKAROUND_REPEAT_TLBI:
6060
return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI);
6161
case ARM64_WORKAROUND_SPECULATIVE_SSBS:
62-
return IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS);
62+
return IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386);
6363
}
6464

6565
return true;

‎arch/arm64/include/asm/cpufeature.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -588,14 +588,14 @@ static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
588588
{
589589
u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL1_SHIFT);
590590

591-
return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
591+
return val == ID_AA64PFR0_EL1_EL1_AARCH32;
592592
}
593593

594594
static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
595595
{
596596
u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL0_SHIFT);
597597

598-
return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
598+
return val == ID_AA64PFR0_EL1_EL0_AARCH32;
599599
}
600600

601601
static inline bool id_aa64pfr0_sve(u64 pfr0)

‎arch/arm64/include/asm/cputype.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,9 +86,12 @@
8686
#define ARM_CPU_PART_CORTEX_X2 0xD48
8787
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
8888
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
89+
#define ARM_CPU_PART_CORTEX_X3 0xD4E
8990
#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
91+
#define ARM_CPU_PART_CORTEX_A720 0xD81
9092
#define ARM_CPU_PART_CORTEX_X4 0xD82
9193
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
94+
#define ARM_CPU_PART_CORTEX_X925 0xD85
9295

9396
#define APM_CPU_PART_XGENE 0x000
9497
#define APM_CPU_VAR_POTENZA 0x00
@@ -162,9 +165,12 @@
162165
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
163166
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
164167
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
168+
#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
165169
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
170+
#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
166171
#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
167172
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
173+
#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
168174
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
169175
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
170176
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

‎arch/arm64/include/asm/esr.h

Lines changed: 27 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,14 @@
121121
#define ESR_ELx_FSC_SECC (0x18)
122122
#define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n))
123123

124+
/* Status codes for individual page table levels */
125+
#define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + n)
126+
#define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + n)
127+
128+
#define ESR_ELx_FSC_FAULT_nL (0x2C)
129+
#define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
130+
ESR_ELx_FSC_FAULT) + (n))
131+
124132
/* ISS field definitions for Data Aborts */
125133
#define ESR_ELx_ISV_SHIFT (24)
126134
#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
@@ -388,20 +396,33 @@ static inline bool esr_is_data_abort(unsigned long esr)
388396

389397
static inline bool esr_fsc_is_translation_fault(unsigned long esr)
390398
{
391-
/* Translation fault, level -1 */
392-
if ((esr & ESR_ELx_FSC) == 0b101011)
393-
return true;
394-
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_FAULT;
399+
esr = esr & ESR_ELx_FSC;
400+
401+
return (esr == ESR_ELx_FSC_FAULT_L(3)) ||
402+
(esr == ESR_ELx_FSC_FAULT_L(2)) ||
403+
(esr == ESR_ELx_FSC_FAULT_L(1)) ||
404+
(esr == ESR_ELx_FSC_FAULT_L(0)) ||
405+
(esr == ESR_ELx_FSC_FAULT_L(-1));
395406
}
396407

397408
static inline bool esr_fsc_is_permission_fault(unsigned long esr)
398409
{
399-
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_PERM;
410+
esr = esr & ESR_ELx_FSC;
411+
412+
return (esr == ESR_ELx_FSC_PERM_L(3)) ||
413+
(esr == ESR_ELx_FSC_PERM_L(2)) ||
414+
(esr == ESR_ELx_FSC_PERM_L(1)) ||
415+
(esr == ESR_ELx_FSC_PERM_L(0));
400416
}
401417

402418
static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
403419
{
404-
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_ACCESS;
420+
esr = esr & ESR_ELx_FSC;
421+
422+
return (esr == ESR_ELx_FSC_ACCESS_L(3)) ||
423+
(esr == ESR_ELx_FSC_ACCESS_L(2)) ||
424+
(esr == ESR_ELx_FSC_ACCESS_L(1)) ||
425+
(esr == ESR_ELx_FSC_ACCESS_L(0));
405426
}
406427

407428
/* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */

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