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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Olof Johansson: "A set of fixes that we've merged late, but for the most part that have been sitting in -next for a while through platform maintainer trees: - Fixes to suspend/resume on Tegra, caused by the added features this merge window - Cleanups and minor fixes to TI additions this merge window - Tee fixes queued up late before the merge window, included here. - A handful of other fixlets There's also a refresh of the shareed config files (multi_v* on 32-bit, and defconfig on 64-bit), to avoid conflicts when we get new contributions" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits) ARM: multi_v7_defconfig: Restore debugfs support ARM: defconfig: re-run savedefconfig on multi_v* configs arm64: defconfig: re-run savedefconfig ARM: pxa: Fix resource properties soc: mediatek: cmdq: fixup wrong input order of write api soc: aspeed: Fix snoop_file_poll()'s return type MAINTAINERS: Switch to Marvell addresses MAINTAINERS: update Cavium ThunderX drivers Revert "arm64: dts: juno: add dma-ranges property" MAINTAINERS: Make Nicolas Saenz Julienne the new bcm2835 maintainer firmware: arm_scmi: Avoid double free in error flow arm64: dts: juno: Fix UART frequency ARM: dts: Fix sgx sysconfig register for omap4 arm: socfpga: execute cold reboot by default ARM: dts: Fix vcsi regulator to be always-on for droid4 to prevent hangs ARM: dts: dra7: fix cpsw mdio fck clock ARM: dts: am57xx-beagle-x15: Update pinmux name to ddr_3_3v ARM: dts: omap3-tao3530: Fix incorrect MMC card detection GPIO polarity soc/tegra: pmc: Add reset sources and levels on Tegra194 soc/tegra: pmc: Add missing IRQ callbacks on Tegra194 ...
2 parents 9888428 + 30f55ea commit 347f56f

32 files changed

+312
-139
lines changed

.mailmap

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@@ -105,6 +105,9 @@ James E Wilson <[email protected]>
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James Ketrenos <jketreno@io.(none)>
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MAINTAINERS

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F: arch/arm/mach-cns3xxx/
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ARM/CAVIUM THUNDER NETWORK DRIVER
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M: Sunil Goutham <sgoutham@cavium.com>
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M: Robert Richter <[email protected]>
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M: Sunil Goutham <sgoutham@marvell.com>
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M: Robert Richter <[email protected]>
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L: [email protected] (moderated for non-subscribers)
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S: Supported
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F: drivers/net/ethernet/cavium/thunder/
@@ -3228,8 +3228,7 @@ N: kona
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F: arch/arm/mach-bcm/
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BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
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M: Eric Anholt <[email protected]>
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M: Stefan Wahren <[email protected]>
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M: Nicolas Saenz Julienne <[email protected]>
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L: [email protected] (moderated for non-subscribers)
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L: [email protected] (moderated for non-subscribers)
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F: drivers/net/wireless/ath/carl9170/
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CAVIUM I2C DRIVER
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M: Jan Glauber <[email protected]>
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M: David Daney <[email protected]>
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W: http://www.cavium.com
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M: Robert Richter <[email protected]>
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W: http://www.marvell.com
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S: Supported
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F: drivers/i2c/busses/i2c-octeon*
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F: drivers/i2c/busses/i2c-thunderx*
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M: Satanand Burla <[email protected]>
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M: Felix Manlunas <[email protected]>
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W: http://www.cavium.com
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W: http://www.marvell.com
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S: Supported
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F: drivers/net/ethernet/cavium/liquidio/
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CAVIUM MMC DRIVER
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M: Jan Glauber <[email protected]>
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M: David Daney <[email protected]>
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M: Steven J. Hill <[email protected]>
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W: http://www.cavium.com
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M: Robert Richter <[email protected]>
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W: http://www.marvell.com
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S: Supported
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F: drivers/mmc/host/cavium*
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CAVIUM OCTEON-TX CRYPTO DRIVER
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M: George Cherian <george.cherian@cavium.com>
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M: George Cherian <gcherian@marvell.com>
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W: http://www.cavium.com
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W: http://www.marvell.com
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F: drivers/crypto/cavium/cpt/
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CAVIUM THUNDERX2 ARM64 SOC
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M: Robert Richter <rrichter@cavium.com>
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M: Robert Richter <rrichter@marvell.com>
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L: [email protected] (moderated for non-subscribers)
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EDAC-CAVIUM OCTEON
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M: David Daney <david.daney@cavium.com>
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M: Robert Richter <rrichter@marvell.com>
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EDAC-CAVIUM THUNDERX
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M: David Daney <[email protected]>
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M: Robert Richter <[email protected]>
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F: drivers/edac/thunderx_edac*
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PCIE DRIVER FOR CAVIUM THUNDERX
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M: David Daney <david.daney@cavium.com>
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M: Robert Richter <rrichter@marvell.com>
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THUNDERX GPIO DRIVER
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M: Robert Richter <rrichter@marvell.com>
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XLP9XX I2C DRIVER
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M: George Cherian <[email protected]>
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F: Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt
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arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts

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};
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&mmc2 {
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pinctrl-names = "default", "hs", "ddr_1_8v";
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pinctrl-names = "default", "hs", "ddr_3_3v";
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pinctrl-0 = <&mmc2_pins_default>;
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pinctrl-1 = <&mmc2_pins_hs>;
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pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;

arch/arm/boot/dts/am57xx-beagle-x15-revc.dts

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};
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&mmc2 {
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pinctrl-names = "default", "hs", "ddr_1_8v";
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pinctrl-names = "default", "hs", "ddr_3_3v";
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pinctrl-0 = <&mmc2_pins_default>;
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pinctrl-1 = <&mmc2_pins_hs>;
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pinctrl-2 = <&mmc2_pins_ddr_rev20>;

arch/arm/boot/dts/bcm2711-rpi-4-b.dts

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reg = <0 0 0>;
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};
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aliases {
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ethernet0 = &genet;
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};
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leds {
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act {
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gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&genet {
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phy-handle = <&phy1>;
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phy-mode = "rgmii-rxid";
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status = "okay";
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};
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&genet_mdio {
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phy1: ethernet-phy@1 {
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/* No PHY interrupt */
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reg = <0x1>;
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};
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};
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/* uart0 communicates with the BT module */
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&uart0 {
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pinctrl-names = "default";

arch/arm/boot/dts/bcm2711.dtsi

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interrupt-parent = <&gicv2>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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/*
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* arm64 reserves the CMA by default somewhere in ZONE_DMA32,
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* that's not good enough for the BCM2711 as some devices can
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* only address the lower 1G of memory (ZONE_DMA).
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*/
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linux,cma {
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compatible = "shared-dma-pool";
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size = <0x2000000>; /* 32MB */
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alloc-ranges = <0x0 0x00000000 0x40000000>;
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reusable;
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linux,cma-default;
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};
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};
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soc {
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/*
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* Defined ranges:
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cpu-release-addr = <0x0 0x000000f0>;
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};
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};
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scb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
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genet: ethernet@7d580000 {
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compatible = "brcm,bcm2711-genet-v5";
338+
reg = <0x0 0x7d580000 0x10000>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
343+
status = "disabled";
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genet_mdio: mdio@e14 {
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compatible = "brcm,genet-mdio-v5";
347+
reg = <0xe14 0x8>;
348+
reg-names = "mdio";
349+
#address-cells = <0x0>;
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#size-cells = <0x1>;
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};
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};
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};
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};
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&clk_osc {

arch/arm/boot/dts/dra7-l4.dtsi

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davinci_mdio: mdio@1000 {
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3059-
clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3059+
clocks = <&gmac_main_clk>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;

arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts

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#include "logicpd-torpedo-37xx-devkit.dts"
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&lcd0 {
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/* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
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compatible = "logicpd,type28";
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arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi

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};
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&hdqw1w {
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pinctrl-names = "default";
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pinctrl-0 = <&hdq_pins>;
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};
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&vpll2 {
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regulator-always-on;
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lcd0: display {
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compatible = "newhaven,nhd-4.3-480272ef-atxl";
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label = "15";
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pinctrl-names = "default";
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169174
>;
170175
};
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177+
hdq_pins: hdq_pins {
178+
pinctrl-single,pins = <
179+
OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */
180+
>;
181+
};
182+
172183
pwm_pins: pinmux_pwm_pins {
173184
pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */

arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi

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regulator-enable-ramp-delay = <1000>;
163163
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/* Used by DSS */
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/* Used by DSS and is the "zerov_regulator" trigger for SoC off mode */
166166
vcsi: VCSI {
167167
regulator-min-microvolt = <1800000>;
168168
regulator-max-microvolt = <1800000>;
169169
regulator-enable-ramp-delay = <1000>;
170-
regulator-boot-on;
170+
regulator-always-on;
171171
};
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173173
vdac: VDAC {

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