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kliteynSaeed Mahameed
kliteyn
authored and
Saeed Mahameed
committed
net/mlx5: Added missing mlx5_ifc definition for HW Steering
Add mlx5_ifc definitions that are required for HWS support. Note that due to change in the mlx5_ifc_flow_table_context_bits structure that now includes both SWS and HWS bits in a union, this patch also includes small change in one of SWS files that was required for compilation. Reviewed-by: Hamdan Agbariya <[email protected]> Signed-off-by: Yevgeny Kliteynik <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]>
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-34
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2 files changed

+167
-34
lines changed

‎drivers/net/ethernet/mellanox/mlx5/core/steering/dr_cmd.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -251,9 +251,9 @@ int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev,
251251
output->level = MLX5_GET(query_flow_table_out, out, flow_table_context.level);
252252

253253
output->sw_owner_icm_root_1 = MLX5_GET64(query_flow_table_out, out,
254-
flow_table_context.sw_owner_icm_root_1);
254+
flow_table_context.sws.sw_owner_icm_root_1);
255255
output->sw_owner_icm_root_0 = MLX5_GET64(query_flow_table_out, out,
256-
flow_table_context.sw_owner_icm_root_0);
256+
flow_table_context.sws.sw_owner_icm_root_0);
257257

258258
return 0;
259259
}
@@ -480,15 +480,15 @@ int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev,
480480
*/
481481
if (attr->table_type == MLX5_FLOW_TABLE_TYPE_NIC_RX) {
482482
MLX5_SET64(flow_table_context, ft_mdev,
483-
sw_owner_icm_root_0, attr->icm_addr_rx);
483+
sws.sw_owner_icm_root_0, attr->icm_addr_rx);
484484
} else if (attr->table_type == MLX5_FLOW_TABLE_TYPE_NIC_TX) {
485485
MLX5_SET64(flow_table_context, ft_mdev,
486-
sw_owner_icm_root_0, attr->icm_addr_tx);
486+
sws.sw_owner_icm_root_0, attr->icm_addr_tx);
487487
} else if (attr->table_type == MLX5_FLOW_TABLE_TYPE_FDB) {
488488
MLX5_SET64(flow_table_context, ft_mdev,
489-
sw_owner_icm_root_0, attr->icm_addr_rx);
489+
sws.sw_owner_icm_root_0, attr->icm_addr_rx);
490490
MLX5_SET64(flow_table_context, ft_mdev,
491-
sw_owner_icm_root_1, attr->icm_addr_tx);
491+
sws.sw_owner_icm_root_1, attr->icm_addr_tx);
492492
}
493493
}
494494

‎include/linux/mlx5/mlx5_ifc.h

Lines changed: 161 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -80,23 +80,15 @@ enum {
8080

8181
enum {
8282
MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83-
MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23,
84-
};
85-
86-
enum {
87-
MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
88-
MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
89-
MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
90-
MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
91-
(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
92-
MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
93-
};
94-
95-
enum {
9683
MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
9784
MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
9885
MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
9986
MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87+
MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23,
88+
MLX5_OBJ_TYPE_STC = 0x0040,
89+
MLX5_OBJ_TYPE_RTC = 0x0041,
90+
MLX5_OBJ_TYPE_STE = 0x0042,
91+
MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
10092
MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
10193
MLX5_OBJ_TYPE_MKEY = 0xff01,
10294
MLX5_OBJ_TYPE_QP = 0xff02,
@@ -112,6 +104,16 @@ enum {
112104
MLX5_OBJ_TYPE_RQT = 0xff0e,
113105
MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
114106
MLX5_OBJ_TYPE_CQ = 0xff10,
107+
MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108+
};
109+
110+
enum {
111+
MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112+
MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113+
MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114+
MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115+
(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116+
MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
115117
};
116118

117119
enum {
@@ -313,6 +315,7 @@ enum {
313315
MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
314316
MLX5_CMD_OP_SYNC_CRYPTO = 0xb12,
315317
MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16,
318+
MLX5_CMD_OP_GENERATE_WQE = 0xb17,
316319
MLX5_CMD_OP_MAX
317320
};
318321

@@ -485,7 +488,13 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
485488
u8 reserved_at_66[0x2];
486489
u8 reformat_add_macsec[0x1];
487490
u8 reformat_remove_macsec[0x1];
488-
u8 reserved_at_6a[0xe];
491+
u8 reparse[0x1];
492+
u8 reserved_at_6b[0x1];
493+
u8 cross_vhca_object[0x1];
494+
u8 reformat_l2_to_l3_audp_tunnel[0x1];
495+
u8 reformat_l3_audp_tunnel_to_l2[0x1];
496+
u8 ignore_flow_level_rtc_valid[0x1];
497+
u8 reserved_at_70[0x8];
489498
u8 log_max_ft_num[0x8];
490499

491500
u8 reserved_at_80[0x10];
@@ -522,7 +531,15 @@ struct mlx5_ifc_ipv6_layout_bits {
522531
u8 ipv6[16][0x8];
523532
};
524533

534+
struct mlx5_ifc_ipv6_simple_layout_bits {
535+
u8 ipv6_127_96[0x20];
536+
u8 ipv6_95_64[0x20];
537+
u8 ipv6_63_32[0x20];
538+
u8 ipv6_31_0[0x20];
539+
};
540+
525541
union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
542+
struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
526543
struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
527544
struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
528545
u8 reserved_at_0[0x80];
@@ -911,7 +928,9 @@ struct mlx5_ifc_flow_table_eswitch_cap_bits {
911928
u8 reserved_at_8[0x5];
912929
u8 fdb_uplink_hairpin[0x1];
913930
u8 fdb_multi_path_any_table_limit_regc[0x1];
914-
u8 reserved_at_f[0x3];
931+
u8 reserved_at_f[0x1];
932+
u8 fdb_dynamic_tunnel[0x1];
933+
u8 reserved_at_11[0x1];
915934
u8 fdb_multi_path_any_table[0x1];
916935
u8 reserved_at_13[0x2];
917936
u8 fdb_modify_header_fwd_to_table[0x1];
@@ -950,6 +969,73 @@ struct mlx5_ifc_flow_table_eswitch_cap_bits {
950969
u8 reserved_at_1900[0x6700];
951970
};
952971

972+
struct mlx5_ifc_wqe_based_flow_table_cap_bits {
973+
u8 reserved_at_0[0x3];
974+
u8 log_max_num_ste[0x5];
975+
u8 reserved_at_8[0x3];
976+
u8 log_max_num_stc[0x5];
977+
u8 reserved_at_10[0x3];
978+
u8 log_max_num_rtc[0x5];
979+
u8 reserved_at_18[0x3];
980+
u8 log_max_num_header_modify_pattern[0x5];
981+
982+
u8 rtc_hash_split_table[0x1];
983+
u8 rtc_linear_lookup_table[0x1];
984+
u8 reserved_at_22[0x1];
985+
u8 stc_alloc_log_granularity[0x5];
986+
u8 reserved_at_28[0x3];
987+
u8 stc_alloc_log_max[0x5];
988+
u8 reserved_at_30[0x3];
989+
u8 ste_alloc_log_granularity[0x5];
990+
u8 reserved_at_38[0x3];
991+
u8 ste_alloc_log_max[0x5];
992+
993+
u8 reserved_at_40[0xb];
994+
u8 rtc_reparse_mode[0x5];
995+
u8 reserved_at_50[0x3];
996+
u8 rtc_index_mode[0x5];
997+
u8 reserved_at_58[0x3];
998+
u8 rtc_log_depth_max[0x5];
999+
1000+
u8 reserved_at_60[0x10];
1001+
u8 ste_format[0x10];
1002+
1003+
u8 stc_action_type[0x80];
1004+
1005+
u8 header_insert_type[0x10];
1006+
u8 header_remove_type[0x10];
1007+
1008+
u8 trivial_match_definer[0x20];
1009+
1010+
u8 reserved_at_140[0x1b];
1011+
u8 rtc_max_num_hash_definer_gen_wqe[0x5];
1012+
1013+
u8 reserved_at_160[0x18];
1014+
u8 access_index_mode[0x8];
1015+
1016+
u8 reserved_at_180[0x10];
1017+
u8 ste_format_gen_wqe[0x10];
1018+
1019+
u8 linear_match_definer_reg_c3[0x20];
1020+
1021+
u8 fdb_jump_to_tir_stc[0x1];
1022+
u8 reserved_at_1c1[0x1f];
1023+
};
1024+
1025+
struct mlx5_ifc_esw_cap_bits {
1026+
u8 reserved_at_0[0x1d];
1027+
u8 merged_eswitch[0x1];
1028+
u8 reserved_at_1e[0x2];
1029+
1030+
u8 reserved_at_20[0x40];
1031+
1032+
u8 esw_manager_vport_number_valid[0x1];
1033+
u8 reserved_at_61[0xf];
1034+
u8 esw_manager_vport_number[0x10];
1035+
1036+
u8 reserved_at_80[0x780];
1037+
};
1038+
9531039
enum {
9541040
MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
9551041
MLX5_COUNTER_FLOW_ESWITCH = 0x1,
@@ -1443,9 +1529,13 @@ enum {
14431529
};
14441530

14451531
enum {
1532+
MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0,
1533+
MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1,
1534+
MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2,
14461535
MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
14471536
MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
14481537
MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
1538+
MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6,
14491539
MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
14501540
MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
14511541
MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
@@ -1650,7 +1740,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
16501740
u8 pci_sync_for_fw_update_event[0x1];
16511741
u8 reserved_at_1f2[0x6];
16521742
u8 init2_lag_tx_port_affinity[0x1];
1653-
u8 reserved_at_1fa[0x3];
1743+
u8 reserved_at_1fa[0x2];
1744+
u8 wqe_based_flow_table_update_cap[0x1];
16541745
u8 cqe_version[0x4];
16551746

16561747
u8 compact_address_vector[0x1];
@@ -1959,7 +2050,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
19592050

19602051
u8 reserved_at_760[0x3];
19612052
u8 log_max_num_header_modify_argument[0x5];
1962-
u8 reserved_at_768[0x4];
2053+
u8 log_header_modify_argument_granularity_offset[0x4];
19632054
u8 log_header_modify_argument_granularity[0x4];
19642055
u8 reserved_at_770[0x3];
19652056
u8 log_header_modify_argument_max_alloc[0x5];
@@ -2006,7 +2097,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
20062097
u8 reserved_at_140[0x60];
20072098

20082099
u8 flow_table_type_2_type[0x8];
2009-
u8 reserved_at_1a8[0x3];
2100+
u8 reserved_at_1a8[0x2];
2101+
u8 format_select_dw_8_6_ext[0x1];
20102102
u8 log_min_mkey_entity_size[0x5];
20112103
u8 reserved_at_1b0[0x10];
20122104

@@ -2022,6 +2114,16 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
20222114
u8 reserved_at_250[0x10];
20232115

20242116
u8 reserved_at_260[0x120];
2117+
2118+
u8 format_select_dw_gtpu_dw_0[0x8];
2119+
u8 format_select_dw_gtpu_dw_1[0x8];
2120+
u8 format_select_dw_gtpu_dw_2[0x8];
2121+
u8 format_select_dw_gtpu_first_ext_dw_0[0x8];
2122+
2123+
u8 generate_wqe_type[0x20];
2124+
2125+
u8 reserved_at_2c0[0xc0];
2126+
20252127
u8 reserved_at_380[0xb];
20262128
u8 min_mkey_log_entity_size_fixed_buffer[0x5];
20272129
u8 ec_vf_vport_base[0x10];
@@ -2037,9 +2139,11 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
20372139

20382140
u8 reserved_at_400[0x1];
20392141
u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2040-
u8 reserved_at_402[0x1e];
2142+
u8 reserved_at_402[0xe];
2143+
u8 return_reg_id[0x10];
20412144

2042-
u8 reserved_at_420[0x20];
2145+
u8 reserved_at_420[0x1c];
2146+
u8 flow_table_hash_type[0x4];
20432147

20442148
u8 reserved_at_440[0x8];
20452149
u8 max_num_eqs_24b[0x18];
@@ -2086,7 +2190,7 @@ struct mlx5_ifc_extended_dest_format_bits {
20862190
u8 reserved_at_60[0x20];
20872191
};
20882192

2089-
union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2193+
union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
20902194
struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
20912195
struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
20922196
};
@@ -2178,7 +2282,10 @@ struct mlx5_ifc_wq_bits {
21782282
u8 reserved_at_139[0x4];
21792283
u8 log_wqe_stride_size[0x3];
21802284

2181-
u8 reserved_at_140[0x80];
2285+
u8 dbr_umem_id[0x20];
2286+
u8 wq_umem_id[0x20];
2287+
2288+
u8 wq_umem_offset[0x40];
21822289

21832290
u8 headers_mkey[0x20];
21842291

@@ -3562,6 +3669,8 @@ union mlx5_ifc_hca_cap_union_bits {
35623669
struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
35633670
struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
35643671
struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3672+
struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3673+
struct mlx5_ifc_esw_cap_bits esw_cap;
35653674
struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
35663675
struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
35673676
struct mlx5_ifc_qos_cap_bits qos_cap;
@@ -3678,7 +3787,7 @@ struct mlx5_ifc_flow_context_bits {
36783787

36793788
u8 reserved_at_1300[0x500];
36803789

3681-
union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3790+
union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
36823791
};
36833792

36843793
enum {
@@ -3919,7 +4028,8 @@ struct mlx5_ifc_sqc_bits {
39194028
u8 reg_umr[0x1];
39204029
u8 allow_swp[0x1];
39214030
u8 hairpin[0x1];
3922-
u8 reserved_at_f[0xb];
4031+
u8 non_wire[0x1];
4032+
u8 reserved_at_10[0xa];
39234033
u8 ts_format[0x2];
39244034
u8 reserved_at_1c[0x4];
39254035

@@ -4961,6 +5071,16 @@ struct mlx5_ifc_set_fte_in_bits {
49615071
struct mlx5_ifc_flow_context_bits flow_context;
49625072
};
49635073

5074+
struct mlx5_ifc_dest_format_bits {
5075+
u8 destination_type[0x8];
5076+
u8 destination_id[0x18];
5077+
5078+
u8 destination_eswitch_owner_vhca_id_valid[0x1];
5079+
u8 packet_reformat[0x1];
5080+
u8 reserved_at_22[0xe];
5081+
u8 destination_eswitch_owner_vhca_id[0x10];
5082+
};
5083+
49645084
struct mlx5_ifc_rts2rts_qp_out_bits {
49655085
u8 status[0x8];
49665086
u8 reserved_at_8[0x18];
@@ -6127,7 +6247,8 @@ struct mlx5_ifc_flow_table_context_bits {
61276247
u8 termination_table[0x1];
61286248
u8 table_miss_action[0x4];
61296249
u8 level[0x8];
6130-
u8 reserved_at_10[0x8];
6250+
u8 rtc_valid[0x1];
6251+
u8 reserved_at_11[0x7];
61316252
u8 log_size[0x8];
61326253

61336254
u8 reserved_at_20[0x8];
@@ -6137,11 +6258,21 @@ struct mlx5_ifc_flow_table_context_bits {
61376258
u8 lag_master_next_table_id[0x18];
61386259

61396260
u8 reserved_at_60[0x60];
6261+
union {
6262+
struct {
6263+
u8 sw_owner_icm_root_1[0x40];
6264+
6265+
u8 sw_owner_icm_root_0[0x40];
6266+
} sws;
6267+
struct {
6268+
u8 rtc_id_0[0x20];
61406269

6141-
u8 sw_owner_icm_root_1[0x40];
6270+
u8 rtc_id_1[0x20];
61426271

6143-
u8 sw_owner_icm_root_0[0x40];
6272+
u8 reserved_at_100[0x40];
61446273

6274+
} hws;
6275+
};
61456276
};
61466277

61476278
struct mlx5_ifc_query_flow_table_out_bits {
@@ -8923,7 +9054,9 @@ struct mlx5_ifc_create_qp_in_bits {
89239054

89249055
struct mlx5_ifc_qpc_bits qpc;
89259056

8926-
u8 reserved_at_800[0x60];
9057+
u8 wq_umem_offset[0x40];
9058+
9059+
u8 wq_umem_id[0x20];
89279060

89289061
u8 wq_umem_valid[0x1];
89299062
u8 reserved_at_861[0x1f];

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