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konradybcioGeorgi Djakov
konradybcio
authored and
Georgi Djakov
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interconnect: qcom: sdm845: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Georgi Djakov <[email protected]>
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‎drivers/interconnect/qcom/sdm845.c

Lines changed: 249 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1263,34 +1263,255 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
12631263
.buswidth = 8,
12641264
};
12651265

1266-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1267-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1268-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1269-
DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
1270-
DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
1271-
DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
1272-
DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
1273-
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
1274-
DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
1275-
DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
1276-
DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
1277-
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
1278-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1279-
DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
1280-
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
1281-
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
1282-
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
1283-
DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
1284-
DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem);
1285-
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
1286-
DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg);
1287-
DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie);
1288-
DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3);
1289-
DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc);
1290-
DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc);
1291-
DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic);
1292-
DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc);
1293-
DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc);
1266+
static struct qcom_icc_bcm bcm_acv = {
1267+
.name = "ACV",
1268+
.keepalive = false,
1269+
.num_nodes = 1,
1270+
.nodes = { &ebi },
1271+
};
1272+
1273+
static struct qcom_icc_bcm bcm_mc0 = {
1274+
.name = "MC0",
1275+
.keepalive = true,
1276+
.num_nodes = 1,
1277+
.nodes = { &ebi },
1278+
};
1279+
1280+
static struct qcom_icc_bcm bcm_sh0 = {
1281+
.name = "SH0",
1282+
.keepalive = true,
1283+
.num_nodes = 1,
1284+
.nodes = { &qns_llcc },
1285+
};
1286+
1287+
static struct qcom_icc_bcm bcm_mm0 = {
1288+
.name = "MM0",
1289+
.keepalive = false,
1290+
.num_nodes = 1,
1291+
.nodes = { &qns_mem_noc_hf },
1292+
};
1293+
1294+
static struct qcom_icc_bcm bcm_sh1 = {
1295+
.name = "SH1",
1296+
.keepalive = false,
1297+
.num_nodes = 1,
1298+
.nodes = { &qns_apps_io },
1299+
};
1300+
1301+
static struct qcom_icc_bcm bcm_mm1 = {
1302+
.name = "MM1",
1303+
.keepalive = true,
1304+
.num_nodes = 7,
1305+
.nodes = { &qxm_camnoc_hf0_uncomp,
1306+
&qxm_camnoc_hf1_uncomp,
1307+
&qxm_camnoc_sf_uncomp,
1308+
&qxm_camnoc_hf0,
1309+
&qxm_camnoc_hf1,
1310+
&qxm_mdp0,
1311+
&qxm_mdp1
1312+
},
1313+
};
1314+
1315+
static struct qcom_icc_bcm bcm_sh2 = {
1316+
.name = "SH2",
1317+
.keepalive = false,
1318+
.num_nodes = 1,
1319+
.nodes = { &qns_memnoc_snoc },
1320+
};
1321+
1322+
static struct qcom_icc_bcm bcm_mm2 = {
1323+
.name = "MM2",
1324+
.keepalive = false,
1325+
.num_nodes = 1,
1326+
.nodes = { &qns2_mem_noc },
1327+
};
1328+
1329+
static struct qcom_icc_bcm bcm_sh3 = {
1330+
.name = "SH3",
1331+
.keepalive = false,
1332+
.num_nodes = 1,
1333+
.nodes = { &acm_tcu },
1334+
};
1335+
1336+
static struct qcom_icc_bcm bcm_mm3 = {
1337+
.name = "MM3",
1338+
.keepalive = false,
1339+
.num_nodes = 5,
1340+
.nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
1341+
};
1342+
1343+
static struct qcom_icc_bcm bcm_sh5 = {
1344+
.name = "SH5",
1345+
.keepalive = false,
1346+
.num_nodes = 1,
1347+
.nodes = { &qnm_apps },
1348+
};
1349+
1350+
static struct qcom_icc_bcm bcm_sn0 = {
1351+
.name = "SN0",
1352+
.keepalive = true,
1353+
.num_nodes = 1,
1354+
.nodes = { &qns_memnoc_sf },
1355+
};
1356+
1357+
static struct qcom_icc_bcm bcm_ce0 = {
1358+
.name = "CE0",
1359+
.keepalive = false,
1360+
.num_nodes = 1,
1361+
.nodes = { &qxm_crypto },
1362+
};
1363+
1364+
static struct qcom_icc_bcm bcm_cn0 = {
1365+
.name = "CN0",
1366+
.keepalive = false,
1367+
.num_nodes = 47,
1368+
.nodes = { &qhm_spdm,
1369+
&qhm_tic,
1370+
&qnm_snoc,
1371+
&xm_qdss_dap,
1372+
&qhs_a1_noc_cfg,
1373+
&qhs_a2_noc_cfg,
1374+
&qhs_aop,
1375+
&qhs_aoss,
1376+
&qhs_camera_cfg,
1377+
&qhs_clk_ctl,
1378+
&qhs_compute_dsp_cfg,
1379+
&qhs_cpr_cx,
1380+
&qhs_crypto0_cfg,
1381+
&qhs_dcc_cfg,
1382+
&qhs_ddrss_cfg,
1383+
&qhs_display_cfg,
1384+
&qhs_glm,
1385+
&qhs_gpuss_cfg,
1386+
&qhs_imem_cfg,
1387+
&qhs_ipa,
1388+
&qhs_mnoc_cfg,
1389+
&qhs_pcie0_cfg,
1390+
&qhs_pcie_gen3_cfg,
1391+
&qhs_pdm,
1392+
&qhs_phy_refgen_south,
1393+
&qhs_pimem_cfg,
1394+
&qhs_prng,
1395+
&qhs_qdss_cfg,
1396+
&qhs_qupv3_north,
1397+
&qhs_qupv3_south,
1398+
&qhs_sdc2,
1399+
&qhs_sdc4,
1400+
&qhs_snoc_cfg,
1401+
&qhs_spdm,
1402+
&qhs_spss_cfg,
1403+
&qhs_tcsr,
1404+
&qhs_tlmm_north,
1405+
&qhs_tlmm_south,
1406+
&qhs_tsif,
1407+
&qhs_ufs_card_cfg,
1408+
&qhs_ufs_mem_cfg,
1409+
&qhs_usb3_0,
1410+
&qhs_usb3_1,
1411+
&qhs_venus_cfg,
1412+
&qhs_vsense_ctrl_cfg,
1413+
&qns_cnoc_a2noc,
1414+
&srvc_cnoc
1415+
},
1416+
};
1417+
1418+
static struct qcom_icc_bcm bcm_qup0 = {
1419+
.name = "QUP0",
1420+
.keepalive = false,
1421+
.num_nodes = 2,
1422+
.nodes = { &qhm_qup1, &qhm_qup2 },
1423+
};
1424+
1425+
static struct qcom_icc_bcm bcm_sn1 = {
1426+
.name = "SN1",
1427+
.keepalive = false,
1428+
.num_nodes = 1,
1429+
.nodes = { &qxs_imem },
1430+
};
1431+
1432+
static struct qcom_icc_bcm bcm_sn2 = {
1433+
.name = "SN2",
1434+
.keepalive = false,
1435+
.num_nodes = 1,
1436+
.nodes = { &qns_memnoc_gc },
1437+
};
1438+
1439+
static struct qcom_icc_bcm bcm_sn3 = {
1440+
.name = "SN3",
1441+
.keepalive = false,
1442+
.num_nodes = 1,
1443+
.nodes = { &qns_cnoc },
1444+
};
1445+
1446+
static struct qcom_icc_bcm bcm_sn4 = {
1447+
.name = "SN4",
1448+
.keepalive = false,
1449+
.num_nodes = 1,
1450+
.nodes = { &qxm_pimem },
1451+
};
1452+
1453+
static struct qcom_icc_bcm bcm_sn5 = {
1454+
.name = "SN5",
1455+
.keepalive = false,
1456+
.num_nodes = 1,
1457+
.nodes = { &xs_qdss_stm },
1458+
};
1459+
1460+
static struct qcom_icc_bcm bcm_sn6 = {
1461+
.name = "SN6",
1462+
.keepalive = false,
1463+
.num_nodes = 3,
1464+
.nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg },
1465+
};
1466+
1467+
static struct qcom_icc_bcm bcm_sn7 = {
1468+
.name = "SN7",
1469+
.keepalive = false,
1470+
.num_nodes = 1,
1471+
.nodes = { &qxs_pcie },
1472+
};
1473+
1474+
static struct qcom_icc_bcm bcm_sn8 = {
1475+
.name = "SN8",
1476+
.keepalive = false,
1477+
.num_nodes = 1,
1478+
.nodes = { &qxs_pcie_gen3 },
1479+
};
1480+
1481+
static struct qcom_icc_bcm bcm_sn9 = {
1482+
.name = "SN9",
1483+
.keepalive = false,
1484+
.num_nodes = 2,
1485+
.nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc },
1486+
};
1487+
1488+
static struct qcom_icc_bcm bcm_sn11 = {
1489+
.name = "SN11",
1490+
.keepalive = false,
1491+
.num_nodes = 2,
1492+
.nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc },
1493+
};
1494+
1495+
static struct qcom_icc_bcm bcm_sn12 = {
1496+
.name = "SN12",
1497+
.keepalive = false,
1498+
.num_nodes = 2,
1499+
.nodes = { &qnm_gladiator_sodv, &xm_gic },
1500+
};
1501+
1502+
static struct qcom_icc_bcm bcm_sn14 = {
1503+
.name = "SN14",
1504+
.keepalive = false,
1505+
.num_nodes = 1,
1506+
.nodes = { &qnm_pcie_anoc },
1507+
};
1508+
1509+
static struct qcom_icc_bcm bcm_sn15 = {
1510+
.name = "SN15",
1511+
.keepalive = false,
1512+
.num_nodes = 1,
1513+
.nodes = { &qnm_memnoc },
1514+
};
12941515

12951516
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
12961517
&bcm_sn9,

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