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clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the SD clocks on R-Car Gen3 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. This includes implementing range checking. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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drivers/clk/renesas/rcar-gen3-cpg.c

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -315,28 +315,33 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
315315
clock->div_table[clock->cur_div_idx].div);
316316
}
317317

318-
static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
319-
unsigned long *parent_rate)
318+
static int cpg_sd_clock_determine_rate(struct clk_hw *hw,
319+
struct clk_rate_request *req)
320320
{
321321
unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX;
322322
struct sd_clock *clock = to_sd_clock(hw);
323323
unsigned long calc_rate, diff;
324324
unsigned int i;
325325

326326
for (i = 0; i < clock->div_num; i++) {
327-
calc_rate = DIV_ROUND_CLOSEST(*parent_rate,
327+
calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate,
328328
clock->div_table[i].div);
329-
diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate;
329+
if (calc_rate < req->min_rate || calc_rate > req->max_rate)
330+
continue;
331+
332+
diff = calc_rate > req->rate ? calc_rate - req->rate
333+
: req->rate - calc_rate;
330334
if (diff < diff_min) {
331335
best_rate = calc_rate;
332336
diff_min = diff;
333337
}
334338
}
335339

336-
if (best_rate > LONG_MAX)
340+
if (best_rate == ULONG_MAX)
337341
return -EINVAL;
338342

339-
return best_rate;
343+
req->rate = best_rate;
344+
return 0;
340345
}
341346

342347
static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -367,7 +372,7 @@ static const struct clk_ops cpg_sd_clock_ops = {
367372
.disable = cpg_sd_clock_disable,
368373
.is_enabled = cpg_sd_clock_is_enabled,
369374
.recalc_rate = cpg_sd_clock_recalc_rate,
370-
.round_rate = cpg_sd_clock_round_rate,
375+
.determine_rate = cpg_sd_clock_determine_rate,
371376
.set_rate = cpg_sd_clock_set_rate,
372377
};
373378

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