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| 1 | +# SPDX-License-Identifier: GPL-2.0 |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Freescale IMX8MP IOMUX Controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + |
| 11 | + |
| 12 | +description: |
| 13 | + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory |
| 14 | + for common binding part and usage. |
| 15 | + |
| 16 | +properties: |
| 17 | + compatible: |
| 18 | + const: fsl,imx8mp-iomuxc |
| 19 | + |
| 20 | + reg: |
| 21 | + maxItems: 1 |
| 22 | + |
| 23 | +# Client device subnode's properties |
| 24 | +patternProperties: |
| 25 | + 'grp$': |
| 26 | + type: object |
| 27 | + description: |
| 28 | + Pinctrl node's client devices use subnodes for desired pin configuration. |
| 29 | + Client device subnodes use below standard properties. |
| 30 | + |
| 31 | + properties: |
| 32 | + fsl,pins: |
| 33 | + allOf: |
| 34 | + - $ref: /schemas/types.yaml#/definitions/uint32-array |
| 35 | + description: |
| 36 | + each entry consists of 6 integers and represents the mux and config |
| 37 | + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg |
| 38 | + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can |
| 39 | + be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last |
| 40 | + integer CONFIG is the pad setting value like pull-up on this pin. Please |
| 41 | + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. |
| 42 | + |
| 43 | + required: |
| 44 | + - fsl,pins |
| 45 | + |
| 46 | + additionalProperties: false |
| 47 | + |
| 48 | +required: |
| 49 | + - compatible |
| 50 | + - reg |
| 51 | + |
| 52 | +additionalProperties: false |
| 53 | + |
| 54 | +examples: |
| 55 | + # Pinmux controller node |
| 56 | + - | |
| 57 | + iomuxc: pinctrl@30330000 { |
| 58 | + compatible = "fsl,imx8mp-iomuxc"; |
| 59 | + reg = <0x30330000 0x10000>; |
| 60 | +
|
| 61 | + pinctrl_uart2: uart2grp { |
| 62 | + fsl,pins = < |
| 63 | + 0x228 0x488 0x5F0 0x0 0x6 0x49 |
| 64 | + 0x228 0x488 0x000 0x0 0x0 0x49 |
| 65 | + >; |
| 66 | + }; |
| 67 | + }; |
| 68 | +
|
| 69 | +... |
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