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Merge tag 'drm-intel-fixes-2020-07-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v5.8-rc4: - GVT fixes - Include asm sources for render cache clear batches Signed-off-by: Dave Airlie <[email protected]> From: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎drivers/gpu/drm/i915/gt/shaders/README

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ASM sources for auto generated shaders
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======================================
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The i915/gt/hsw_clear_kernel.c and i915/gt/ivb_clear_kernel.c files contain
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pre-compiled batch chunks that will clear any residual render cache during
6+
context switch.
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They are generated from their respective platform ASM files present on
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i915/gt/shaders/clear_kernel directory.
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The generated .c files should never be modified directly. Instead, any modification
12+
needs to be done on the on their respective ASM files and build instructions below
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needes to be followed.
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Building
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========
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Environment
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-----------
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IGT GPU tool scripts and the Mesa's i965 instruction assembler tool are used
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on building.
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Please make sure your Mesa tool is compiled with "-Dtools=intel" and
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"-Ddri-drivers=i965", and run this script from IGT source root directory"
26+
27+
The instructions bellow assume:
28+
* IGT gpu tools source code is located on your home directory (~) as ~/igt
29+
* Mesa source code is located on your home directory (~) as ~/mesa
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and built under the ~/mesa/build directory
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* Linux kernel source code is under your home directory (~) as ~/linux
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Instructions
34+
------------
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~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm \
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~/igt/lib/i915/shaders/clear_kernel/ivb.asm
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~ $ cd ~/igt
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igt $ ./scripts/generate_clear_kernel.sh -g ivb \
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-m ~/mesa/build/src/intel/tools/i965_asm
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~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm \
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~/igt/lib/i915/shaders/clear_kernel/hsw.asm
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~ $ cd ~/igt
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igt $ ./scripts/generate_clear_kernel.sh -g hsw \
46+
-m ~/mesa/build/src/intel/tools/i965_asm

‎drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm

Lines changed: 119 additions & 0 deletions
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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6+
/*
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* Kernel for PAVP buffer clear.
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*
9+
* 1. Clear all 64 GRF registers assigned to the kernel with designated value;
10+
* 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
11+
* 512 bytes of Render Cache.
12+
*/
13+
14+
/* Store designated "clear GRF" value */
15+
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
16+
17+
/**
18+
* Curbe Format
19+
*
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* DW 1.0 - Block Offset to write Render Cache
21+
* DW 1.1 [15:0] - Clear Word
22+
* DW 1.2 - Delay iterations
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* DW 1.3 - Enable Instrumentation (only for debug)
24+
* DW 1.4 - Rsvd (intended for context ID)
25+
* DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26+
* DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
27+
* DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
28+
*
29+
* Binding Table
30+
*
31+
* BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
32+
* BTI 1: Wait/Instrumentation Buffer
33+
* Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
34+
* Expected to be initialized to 0 by driver/another kernel
35+
* Layout:
36+
* RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
37+
* Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
38+
*/
39+
add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
40+
cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
41+
(+f0.0) jmpi(1) 352D { align1 WE_all 1N };
42+
43+
/**
44+
* State Register has info on where this thread is running
45+
* IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
46+
* HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
47+
*/
48+
mov(8) g3<1>UD 0x00000000UD { align1 1Q };
49+
shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
50+
and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
51+
shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
52+
and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
53+
mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
54+
add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
55+
shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
56+
and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
57+
mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
58+
add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
59+
60+
mov(8) g5<1>UD 0x00000000UD { align1 1Q };
61+
and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
62+
mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
63+
64+
mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
65+
mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
66+
mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
67+
mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
68+
and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
69+
70+
/* Media block read to fetch current value at specified location in instrumentation buffer */
71+
sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
72+
73+
render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
74+
add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
75+
76+
/* Media block write for updated value at specified location in instrumentation buffer */
77+
sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
78+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
79+
80+
/* Delay thread for specified parameter */
81+
add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
82+
(+f0.0) jmpi(1) -32D { align1 WE_all 1N };
83+
84+
/* Store designated "clear GRF" value */
85+
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
86+
87+
/* Initialize looping parameters */
88+
mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
89+
mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
90+
91+
/* Write 32x16 all "0" block */
92+
mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
93+
mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
94+
mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
95+
mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
96+
and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
97+
mov(16) g3<1>UD 0x00000000UD { align1 1H };
98+
mov(16) g4<1>UD 0x00000000UD { align1 1H };
99+
mov(16) g5<1>UD 0x00000000UD { align1 1H };
100+
mov(16) g6<1>UD 0x00000000UD { align1 1H };
101+
mov(16) g7<1>UD 0x00000000UD { align1 1H };
102+
mov(16) g8<1>UD 0x00000000UD { align1 1H };
103+
mov(16) g9<1>UD 0x00000000UD { align1 1H };
104+
mov(16) g10<1>UD 0x00000000UD { align1 1H };
105+
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
106+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
107+
add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
108+
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
109+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
110+
111+
/* Now, clear all GRF registers */
112+
add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
113+
mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
114+
add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
115+
(+f0.0) jmpi(1) -64D { align1 WE_all 1N };
116+
117+
/* Terminante the thread */
118+
sendc(8) null<1>UD g127<8,8,1>F 0x82000010
119+
thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };

‎drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm

Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,117 @@
1+
// SPDX-License-Identifier: MIT
2+
/*
3+
* Copyright © 2020 Intel Corporation
4+
*/
5+
6+
/*
7+
* Kernel for PAVP buffer clear.
8+
*
9+
* 1. Clear all 64 GRF registers assigned to the kernel with designated value;
10+
* 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
11+
* 512 bytes of Render Cache.
12+
*/
13+
14+
/* Store designated "clear GRF" value */
15+
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
16+
17+
/**
18+
* Curbe Format
19+
*
20+
* DW 1.0 - Block Offset to write Render Cache
21+
* DW 1.1 [15:0] - Clear Word
22+
* DW 1.2 - Delay iterations
23+
* DW 1.3 - Enable Instrumentation (only for debug)
24+
* DW 1.4 - Rsvd (intended for context ID)
25+
* DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26+
* DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
27+
* DW 1.7 - Rsvd MBZ (inteded for Total Thread Count)
28+
*
29+
* Binding Table
30+
*
31+
* BTI 0: 2D Surface to help clear L3 (Render/Data Cache)
32+
* BTI 1: Wait/Instrumentation Buffer
33+
* Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT)
34+
* Expected to be initialized to 0 by driver/another kernel
35+
* Layout :
36+
* RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS]
37+
* Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N
38+
*/
39+
add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */
40+
cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N };
41+
(+f0.0) jmpi(1) 44D { align1 WE_all 1N };
42+
43+
/**
44+
* State Register has info on where this thread is running
45+
* IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
46+
* HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID
47+
*/
48+
mov(8) g3<1>UD 0x00000000UD { align1 1Q };
49+
shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N };
50+
and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */
51+
shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N };
52+
and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */
53+
mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N };
54+
add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */
55+
shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N };
56+
and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */
57+
mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N };
58+
add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */
59+
60+
mov(8) g5<1>UD 0x00000000UD { align1 1Q };
61+
and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N };
62+
mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N };
63+
64+
mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */
65+
mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */
66+
mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */
67+
mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */
68+
and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N };
69+
70+
/* Media block read to fetch current value at specified location in instrumentation buffer */
71+
sendc(8) g5<1>UD g4<8,8,1>F 0x02190001
72+
render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q };
73+
add(1) g5<1>D g5<0,1,0>D 1D { align1 1N };
74+
75+
/* Media block write for updated value at specified location in instrumentation buffer */
76+
sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001
77+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q };
78+
/* Delay thread for specified parameter */
79+
add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N };
80+
(+f0.0) jmpi(1) -4D { align1 WE_all 1N };
81+
82+
/* Store designated "clear GRF" value */
83+
mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
84+
85+
/* Initialize looping parameters */
86+
mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */
87+
mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */
88+
89+
/* Write 32x16 all "0" block */
90+
mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q };
91+
mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q };
92+
mov(2) g2<1>UD g1<2,2,1>UW { align1 1N };
93+
mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */
94+
and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N };
95+
mov(16) g3<1>UD 0x00000000UD { align1 1H };
96+
mov(16) g4<1>UD 0x00000000UD { align1 1H };
97+
mov(16) g5<1>UD 0x00000000UD { align1 1H };
98+
mov(16) g6<1>UD 0x00000000UD { align1 1H };
99+
mov(16) g7<1>UD 0x00000000UD { align1 1H };
100+
mov(16) g8<1>UD 0x00000000UD { align1 1H };
101+
mov(16) g9<1>UD 0x00000000UD { align1 1H };
102+
mov(16) g10<1>UD 0x00000000UD { align1 1H };
103+
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
104+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
105+
add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N };
106+
sendc(8) null<1>UD g2<8,8,1>F 0x120a8000
107+
render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q };
108+
109+
/* Now, clear all GRF registers */
110+
add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N };
111+
mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H };
112+
add(1) a0<1>D a0<0,1,0>D 32D { align1 1N };
113+
(+f0.0) jmpi(1) -8D { align1 WE_all 1N };
114+
115+
/* Terminante the thread */
116+
sendc(8) null<1>UD g127<8,8,1>F 0x82000010
117+
thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT };

‎drivers/gpu/drm/i915/gvt/debugfs.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ static inline int mmio_diff_handler(struct intel_gvt *gvt,
6666
vreg = vgpu_vreg(param->vgpu, offset);
6767

6868
if (preg != vreg) {
69-
node = kmalloc(sizeof(*node), GFP_KERNEL);
69+
node = kmalloc(sizeof(*node), GFP_ATOMIC);
7070
if (!node)
7171
return -ENOMEM;
7272

‎drivers/gpu/drm/i915/gvt/handlers.c

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1726,13 +1726,13 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
17261726
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
17271727
write_vreg(vgpu, offset, p_data, bytes);
17281728

1729-
if (data & _MASKED_BIT_ENABLE(1)) {
1729+
if (IS_MASKED_BITS_ENABLED(data, 1)) {
17301730
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
17311731
return 0;
17321732
}
17331733

17341734
if (IS_COFFEELAKE(vgpu->gvt->gt->i915) &&
1735-
data & _MASKED_BIT_ENABLE(2)) {
1735+
IS_MASKED_BITS_ENABLED(data, 2)) {
17361736
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
17371737
return 0;
17381738
}
@@ -1741,14 +1741,14 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
17411741
* pvinfo, if not, we will treat this guest as non-gvtg-aware
17421742
* guest, and stop emulating its cfg space, mmio, gtt, etc.
17431743
*/
1744-
if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1745-
(data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1746-
&& !vgpu->pv_notified) {
1744+
if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
1745+
IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
1746+
!vgpu->pv_notified) {
17471747
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
17481748
return 0;
17491749
}
1750-
if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1751-
|| (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1750+
if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
1751+
IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
17521752
enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
17531753

17541754
gvt_dbg_core("EXECLIST %s on ring %s\n",
@@ -1809,7 +1809,7 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
18091809
write_vreg(vgpu, offset, p_data, bytes);
18101810
data = vgpu_vreg(vgpu, offset);
18111811

1812-
if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1812+
if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
18131813
data |= RESET_CTL_READY_TO_RESET;
18141814
else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
18151815
data &= ~RESET_CTL_READY_TO_RESET;
@@ -1827,7 +1827,8 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
18271827
(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
18281828
write_vreg(vgpu, offset, p_data, bytes);
18291829

1830-
if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))
1830+
if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
1831+
IS_MASKED_BITS_ENABLED(data, 0x8))
18311832
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
18321833

18331834
return 0;
@@ -3055,6 +3056,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
30553056
MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
30563057
MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
30573058
MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
3059+
MMIO_D(_MMIO(_PLANE_SURF_3_B), D_SKL_PLUS);
30583060

30593061
MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
30603062
MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
@@ -3131,8 +3133,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
31313133
MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
31323134
NULL, NULL);
31333135

3134-
MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
3135-
MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
3136+
MMIO_D(GAMT_CHKN_BIT_REG, D_KBL | D_CFL);
3137+
MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
31363138

31373139
return 0;
31383140
}

‎drivers/gpu/drm/i915/gvt/mmio_context.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,8 +54,8 @@ bool is_inhibit_context(struct intel_context *ce);
5454

5555
int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
5656
struct i915_request *req);
57-
#define IS_RESTORE_INHIBIT(a) \
58-
(_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) == \
59-
((a) & _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)))
57+
58+
#define IS_RESTORE_INHIBIT(a) \
59+
IS_MASKED_BITS_ENABLED(a, CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)
6060

6161
#endif

‎drivers/gpu/drm/i915/gvt/reg.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,11 @@
9494
#define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
9595
((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
9696

97+
#define IS_MASKED_BITS_ENABLED(_val, _b) \
98+
(((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
99+
#define IS_MASKED_BITS_DISABLED(_val, _b) \
100+
((_val) & _MASKED_BIT_DISABLE(_b))
101+
97102
#define FORCEWAKE_RENDER_GEN9_REG 0xa278
98103
#define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
99104
#define FORCEWAKE_BLITTER_GEN9_REG 0xa188

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