Skip to content

Commit 37e8822

Browse files
committed
Merge tag 'x86-cleanups-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cleanups from Ingo Molnar: "Misc cleanups all around the place" * tag 'x86-cleanups-2020-08-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/ioperm: Initialize pointer bitmap with NULL rather than 0 x86: uv: uv_hub.h: Delete duplicated word x86: cmpxchg_32.h: Delete duplicated word x86: bootparam.h: Delete duplicated word x86/mm: Remove the unused mk_kernel_pgd() #define x86/tsc: Remove unused "US_SCALE" and "NS_SCALE" leftover macros x86/ioapic: Remove unused "IOAPIC_AUTO" define x86/mm: Drop unused MAX_PHYSADDR_BITS x86/msr: Move the F15h MSRs where they belong x86/idt: Make idt_descr static initrd: Remove erroneous comment x86/mm/32: Fix -Wmissing prototypes warnings for init.c cpu/speculation: Add prototype for cpu_show_srbds() x86/mm: Fix -Wmissing-prototypes warnings for arch/x86/mm/init.c x86/asm: Unify __ASSEMBLY__ blocks x86/cpufeatures: Mark two free bits in word 3 x86/msr: Lift AMD family 0x15 power-specific MSRs
2 parents 1ff9b20 + 90fc739 commit 37e8822

File tree

20 files changed

+27
-49
lines changed

20 files changed

+27
-49
lines changed

arch/x86/events/amd/power.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,10 +13,6 @@
1313
#include <asm/cpu_device_id.h>
1414
#include "../perf_event.h"
1515

16-
#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
17-
#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
18-
#define MSR_F15H_PTSC 0xc0010280
19-
2016
/* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */
2117
#define AMD_POWER_EVENT_MASK 0xFFULL
2218

arch/x86/include/asm/asm.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@
144144
_ASM_PTR (entry); \
145145
.popsection
146146

147-
#else
147+
#else /* ! __ASSEMBLY__ */
148148
# define _EXPAND_EXTABLE_HANDLE(x) #x
149149
# define _ASM_EXTABLE_HANDLE(from, to, handler) \
150150
" .pushsection \"__ex_table\",\"a\"\n" \
@@ -164,9 +164,7 @@
164164
_ASM_EXTABLE_HANDLE(from, to, ex_handler_fault)
165165

166166
/* For C file, we already have NOKPROBE_SYMBOL macro */
167-
#endif
168167

169-
#ifndef __ASSEMBLY__
170168
/*
171169
* This output constraint should be used for any inline asm which has a "call"
172170
* instruction. Otherwise the asm may be inserted before the frame pointer
@@ -175,6 +173,6 @@
175173
*/
176174
register unsigned long current_stack_pointer asm(_ASM_SP);
177175
#define ASM_CALL_CONSTRAINT "+r" (current_stack_pointer)
178-
#endif
176+
#endif /* __ASSEMBLY__ */
179177

180178
#endif /* _ASM_X86_ASM_H */

arch/x86/include/asm/cmpxchg_32.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
#define _ASM_X86_CMPXCHG_32_H
44

55
/*
6-
* Note: if you use set64_bit(), __cmpxchg64(), or their variants, you
6+
* Note: if you use set64_bit(), __cmpxchg64(), or their variants,
77
* you need to test for the feature in boot_cpu_data.
88
*/
99

arch/x86/include/asm/cpufeatures.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@
9696
#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */
9797
#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
9898
#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
99+
/* free ( 3*32+17) */
99100
#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
100101
#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
101102
#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
@@ -107,6 +108,7 @@
107108
#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */
108109
#define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */
109110
#define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
111+
/* free ( 3*32+29) */
110112
#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
111113
#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
112114

arch/x86/include/asm/io_apic.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,6 @@ struct IR_IO_APIC_route_entry {
9999
struct irq_alloc_info;
100100
struct ioapic_domain_cfg;
101101

102-
#define IOAPIC_AUTO -1
103102
#define IOAPIC_EDGE 0
104103
#define IOAPIC_LEVEL 1
105104

arch/x86/include/asm/mem_encrypt.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,9 +43,10 @@ void __init sme_enable(struct boot_params *bp);
4343
int __init early_set_memory_decrypted(unsigned long vaddr, unsigned long size);
4444
int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size);
4545

46+
void __init mem_encrypt_free_decrypted_mem(void);
47+
4648
/* Architecture __weak replacement functions */
4749
void __init mem_encrypt_init(void);
48-
void __init mem_encrypt_free_decrypted_mem(void);
4950

5051
bool sme_active(void);
5152
bool sev_active(void);
@@ -77,6 +78,8 @@ early_set_memory_decrypted(unsigned long vaddr, unsigned long size) { return 0;
7778
static inline int __init
7879
early_set_memory_encrypted(unsigned long vaddr, unsigned long size) { return 0; }
7980

81+
static inline void mem_encrypt_free_decrypted_mem(void) { }
82+
8083
#define __bss_decrypted
8184

8285
#endif /* CONFIG_AMD_MEM_ENCRYPT */

arch/x86/include/asm/msr-index.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -434,7 +434,6 @@
434434
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
435435
#define MSR_AMD64_TSC_RATIO 0xc0000104
436436
#define MSR_AMD64_NB_CFG 0xc001001f
437-
#define MSR_AMD64_CPUID_FN_1 0xc0011004
438437
#define MSR_AMD64_PATCH_LOADER 0xc0010020
439438
#define MSR_AMD_PERF_CTL 0xc0010062
440439
#define MSR_AMD_PERF_STATUS 0xc0010063
@@ -443,6 +442,7 @@
443442
#define MSR_AMD64_OSVW_STATUS 0xc0010141
444443
#define MSR_AMD_PPIN_CTL 0xc00102f0
445444
#define MSR_AMD_PPIN 0xc00102f1
445+
#define MSR_AMD64_CPUID_FN_1 0xc0011004
446446
#define MSR_AMD64_LS_CFG 0xc0011020
447447
#define MSR_AMD64_DC_CFG 0xc0011022
448448
#define MSR_AMD64_BU_CFG2 0xc001102a
@@ -482,6 +482,8 @@
482482
#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
483483

484484
/* Fam 15h MSRs */
485+
#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
486+
#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
485487
#define MSR_F15H_PERF_CTL 0xc0010200
486488
#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
487489
#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)

arch/x86/include/asm/pgtable.h

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -999,15 +999,12 @@ extern int direct_gbpages;
999999
void init_mem_mapping(void);
10001000
void early_alloc_pgt_buf(void);
10011001
extern void memblock_find_dma_reserve(void);
1002-
1003-
1004-
#ifdef CONFIG_X86_64
1005-
extern pgd_t trampoline_pgd_entry;
1006-
10071002
void __init poking_init(void);
1008-
10091003
unsigned long init_memory_mapping(unsigned long start,
10101004
unsigned long end, pgprot_t prot);
1005+
1006+
#ifdef CONFIG_X86_64
1007+
extern pgd_t trampoline_pgd_entry;
10111008
#endif
10121009

10131010
/* local pte updates need not use xchg for locking */

arch/x86/include/asm/pgtable_64.h

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -175,16 +175,13 @@ extern void sync_global_pgds(unsigned long start, unsigned long end);
175175
* and a page entry and page directory to the page they refer to.
176176
*/
177177

178-
/*
179-
* Level 4 access.
180-
*/
181-
#define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE)
178+
/* PGD - Level 4 access */
182179

183-
/* PUD - Level3 access */
180+
/* PUD - Level 3 access */
184181

185-
/* PMD - Level 2 access */
182+
/* PMD - Level 2 access */
186183

187-
/* PTE - Level 1 access. */
184+
/* PTE - Level 1 access */
188185

189186
/*
190187
* Encode and de-code a swap entry

arch/x86/include/asm/sparsemem.h

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,24 +10,20 @@
1010
* field of the struct page
1111
*
1212
* SECTION_SIZE_BITS 2^n: size of each section
13-
* MAX_PHYSADDR_BITS 2^n: max size of physical address space
14-
* MAX_PHYSMEM_BITS 2^n: how much memory we can have in that space
13+
* MAX_PHYSMEM_BITS 2^n: max size of physical address space
1514
*
1615
*/
1716

1817
#ifdef CONFIG_X86_32
1918
# ifdef CONFIG_X86_PAE
2019
# define SECTION_SIZE_BITS 29
21-
# define MAX_PHYSADDR_BITS 36
2220
# define MAX_PHYSMEM_BITS 36
2321
# else
2422
# define SECTION_SIZE_BITS 26
25-
# define MAX_PHYSADDR_BITS 32
2623
# define MAX_PHYSMEM_BITS 32
2724
# endif
2825
#else /* CONFIG_X86_32 */
2926
# define SECTION_SIZE_BITS 27 /* matt - 128 is convenient right now */
30-
# define MAX_PHYSADDR_BITS (pgtable_l5_enabled() ? 52 : 44)
3127
# define MAX_PHYSMEM_BITS (pgtable_l5_enabled() ? 52 : 46)
3228
#endif
3329

0 commit comments

Comments
 (0)