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30 | 30 | #define VIG_SC7180_MASK \
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31 | 31 | (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
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32 | 32 |
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33 |
| -#define VIG_SM8250_MASK \ |
34 |
| - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) |
35 |
| - |
36 | 33 | #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
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37 | 34 |
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38 | 35 | #define DMA_MSM8998_MASK \
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@@ -358,7 +355,7 @@ static const struct dpu_caps sc7180_dpu_caps = {
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358 | 355 | static const struct dpu_caps sm6115_dpu_caps = {
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359 | 356 | .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
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360 | 357 | .max_mixer_blendstages = 0x4,
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361 |
| - .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, |
| 358 | + .qseed_type = DPU_SSPP_SCALER_QSEED4, |
362 | 359 | .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
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363 | 360 | .ubwc_version = DPU_HW_UBWC_VER_10,
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364 | 361 | .has_dim_layer = true,
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@@ -1235,10 +1232,10 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
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1235 | 1232 | };
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1236 | 1233 |
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1237 | 1234 | static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
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1238 |
| - _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE); |
| 1235 | + _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); |
1239 | 1236 |
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1240 | 1237 | static const struct dpu_sspp_cfg sm6115_sspp[] = {
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1241 |
| - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, |
| 1238 | + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, |
1242 | 1239 | sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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1243 | 1240 | SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
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1244 | 1241 | sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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