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15 | 15 | #include <linux/platform_device.h>
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16 | 16 | #include <linux/regmap.h>
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17 | 17 | #include <linux/seq_file.h>
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| 18 | +#include <linux/types.h> |
18 | 19 |
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19 | 20 | #define CRYSTALCOVE_GPIO_NUM 16
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20 | 21 | #define CRYSTALCOVE_VGPIO_NUM 95
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@@ -238,34 +239,43 @@ static void crystalcove_bus_sync_unlock(struct irq_data *data)
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238 | 239 |
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239 | 240 | static void crystalcove_irq_unmask(struct irq_data *data)
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240 | 241 | {
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241 |
| - struct crystalcove_gpio *cg = |
242 |
| - gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
| 242 | + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
| 243 | + struct crystalcove_gpio *cg = gpiochip_get_data(gc); |
| 244 | + irq_hw_number_t hwirq = irqd_to_hwirq(data); |
243 | 245 |
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244 |
| - if (data->hwirq < CRYSTALCOVE_GPIO_NUM) { |
245 |
| - cg->set_irq_mask = false; |
246 |
| - cg->update |= UPDATE_IRQ_MASK; |
247 |
| - } |
| 246 | + if (hwirq >= CRYSTALCOVE_GPIO_NUM) |
| 247 | + return; |
| 248 | + |
| 249 | + gpiochip_enable_irq(gc, hwirq); |
| 250 | + |
| 251 | + cg->set_irq_mask = false; |
| 252 | + cg->update |= UPDATE_IRQ_MASK; |
248 | 253 | }
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249 | 254 |
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250 | 255 | static void crystalcove_irq_mask(struct irq_data *data)
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251 | 256 | {
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252 |
| - struct crystalcove_gpio *cg = |
253 |
| - gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
| 257 | + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
| 258 | + struct crystalcove_gpio *cg = gpiochip_get_data(gc); |
| 259 | + irq_hw_number_t hwirq = irqd_to_hwirq(data); |
254 | 260 |
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255 |
| - if (data->hwirq < CRYSTALCOVE_GPIO_NUM) { |
256 |
| - cg->set_irq_mask = true; |
257 |
| - cg->update |= UPDATE_IRQ_MASK; |
258 |
| - } |
| 261 | + if (hwirq >= CRYSTALCOVE_GPIO_NUM) |
| 262 | + return; |
| 263 | + |
| 264 | + cg->set_irq_mask = true; |
| 265 | + cg->update |= UPDATE_IRQ_MASK; |
| 266 | + |
| 267 | + gpiochip_disable_irq(gc, hwirq); |
259 | 268 | }
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260 | 269 |
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261 |
| -static struct irq_chip crystalcove_irqchip = { |
| 270 | +static const struct irq_chip crystalcove_irqchip = { |
262 | 271 | .name = "Crystal Cove",
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263 | 272 | .irq_mask = crystalcove_irq_mask,
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264 | 273 | .irq_unmask = crystalcove_irq_unmask,
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265 | 274 | .irq_set_type = crystalcove_irq_type,
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266 | 275 | .irq_bus_lock = crystalcove_bus_lock,
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267 | 276 | .irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
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268 |
| - .flags = IRQCHIP_SKIP_SET_WAKE, |
| 277 | + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, |
| 278 | + GPIOCHIP_IRQ_RESOURCE_HELPERS, |
269 | 279 | };
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270 | 280 |
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271 | 281 | static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
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@@ -353,7 +363,7 @@ static int crystalcove_gpio_probe(struct platform_device *pdev)
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353 | 363 | cg->regmap = pmic->regmap;
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354 | 364 |
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355 | 365 | girq = &cg->chip.irq;
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356 |
| - girq->chip = &crystalcove_irqchip; |
| 366 | + gpio_irq_chip_set_chip(girq, &crystalcove_irqchip); |
357 | 367 | /* This will let us handle the parent IRQ in the driver */
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358 | 368 | girq->parent_handler = NULL;
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359 | 369 | girq->num_parents = 0;
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