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19 | 19 | * gpio[1]: HOST_GPIO32->HOST_GPIO55
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20 | 20 | */
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21 | 21 | #define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32
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| 22 | +#define MLXBF3_GPIO_MAX_PINS_BLOCK0 32 |
| 23 | +#define MLXBF3_GPIO_MAX_PINS_BLOCK1 24 |
22 | 24 |
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23 | 25 | /*
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24 | 26 | * fw_gpio[x] block registers and their offset
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@@ -158,6 +160,26 @@ static const struct irq_chip gpio_mlxbf3_irqchip = {
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158 | 160 | GPIOCHIP_IRQ_RESOURCE_HELPERS,
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159 | 161 | };
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160 | 162 |
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| 163 | +static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip) |
| 164 | +{ |
| 165 | + unsigned int id; |
| 166 | + |
| 167 | + switch(chip->ngpio) { |
| 168 | + case MLXBF3_GPIO_MAX_PINS_BLOCK0: |
| 169 | + id = 0; |
| 170 | + break; |
| 171 | + case MLXBF3_GPIO_MAX_PINS_BLOCK1: |
| 172 | + id = 1; |
| 173 | + break; |
| 174 | + default: |
| 175 | + return -EINVAL; |
| 176 | + } |
| 177 | + |
| 178 | + return gpiochip_add_pin_range(chip, "MLNXBF34:00", |
| 179 | + chip->base, id * MLXBF3_GPIO_MAX_PINS_PER_BLOCK, |
| 180 | + chip->ngpio); |
| 181 | +} |
| 182 | + |
161 | 183 | static int mlxbf3_gpio_probe(struct platform_device *pdev)
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162 | 184 | {
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163 | 185 | struct device *dev = &pdev->dev;
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@@ -197,6 +219,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev)
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197 | 219 | gc->request = gpiochip_generic_request;
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198 | 220 | gc->free = gpiochip_generic_free;
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199 | 221 | gc->owner = THIS_MODULE;
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| 222 | + gc->add_pin_ranges = mlxbf3_gpio_add_pin_ranges; |
200 | 223 |
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201 | 224 | irq = platform_get_irq(pdev, 0);
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202 | 225 | if (irq >= 0) {
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@@ -243,6 +266,7 @@ static struct platform_driver mlxbf3_gpio_driver = {
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243 | 266 | };
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244 | 267 | module_platform_driver(mlxbf3_gpio_driver);
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245 | 268 |
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| 269 | +MODULE_SOFTDEP("pre: pinctrl-mlxbf3"); |
246 | 270 | MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver");
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247 | 271 | MODULE_AUTHOR( "Asmaa Mnebhi <[email protected]>");
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248 | 272 | MODULE_LICENSE("Dual BSD/GPL");
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