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20 | 20 | #define EIOINTC_BASE 0x1400
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21 | 21 | #define EIOINTC_SIZE 0x900
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22 | 22 |
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| 23 | +#define EIOINTC_NODETYPE_START 0xa0 |
| 24 | +#define EIOINTC_NODETYPE_END 0xbf |
| 25 | +#define EIOINTC_IPMAP_START 0xc0 |
| 26 | +#define EIOINTC_IPMAP_END 0xc7 |
| 27 | +#define EIOINTC_ENABLE_START 0x200 |
| 28 | +#define EIOINTC_ENABLE_END 0x21f |
| 29 | +#define EIOINTC_BOUNCE_START 0x280 |
| 30 | +#define EIOINTC_BOUNCE_END 0x29f |
| 31 | +#define EIOINTC_ISR_START 0x300 |
| 32 | +#define EIOINTC_ISR_END 0x31f |
| 33 | +#define EIOINTC_COREISR_START 0x400 |
| 34 | +#define EIOINTC_COREISR_END 0x41f |
| 35 | +#define EIOINTC_COREMAP_START 0x800 |
| 36 | +#define EIOINTC_COREMAP_END 0x8ff |
| 37 | + |
23 | 38 | #define EIOINTC_VIRT_BASE (0x40000000)
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24 | 39 | #define EIOINTC_VIRT_SIZE (0x1000)
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25 | 40 |
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| 41 | +#define EIOINTC_VIRT_FEATURES (0x0) |
| 42 | +#define EIOINTC_HAS_VIRT_EXTENSION (0) |
| 43 | +#define EIOINTC_HAS_ENABLE_OPTION (1) |
| 44 | +#define EIOINTC_HAS_INT_ENCODE (2) |
| 45 | +#define EIOINTC_HAS_CPU_ENCODE (3) |
| 46 | +#define EIOINTC_VIRT_HAS_FEATURES ((1U << EIOINTC_HAS_VIRT_EXTENSION) \ |
| 47 | + | (1U << EIOINTC_HAS_ENABLE_OPTION) \ |
| 48 | + | (1U << EIOINTC_HAS_INT_ENCODE) \ |
| 49 | + | (1U << EIOINTC_HAS_CPU_ENCODE)) |
| 50 | +#define EIOINTC_VIRT_CONFIG (0x4) |
| 51 | +#define EIOINTC_ENABLE (1) |
| 52 | +#define EIOINTC_ENABLE_INT_ENCODE (2) |
| 53 | +#define EIOINTC_ENABLE_CPU_ENCODE (3) |
| 54 | + |
26 | 55 | #define LOONGSON_IP_NUM 8
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27 | 56 |
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28 | 57 | struct loongarch_eiointc {
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@@ -89,5 +118,6 @@ struct loongarch_eiointc {
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89 | 118 | };
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90 | 119 |
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91 | 120 | int kvm_loongarch_register_eiointc_device(void);
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| 121 | +void eiointc_set_irq(struct loongarch_eiointc *s, int irq, int level); |
92 | 122 |
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93 | 123 | #endif /* __ASM_KVM_EIOINTC_H */
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