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Merge tag 'x86-urgent-2024-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar: - Fix regressions of the new x86 CPU VFM (vendor/family/model) enumeration/matching code - Fix crash kernel detection on buggy firmware with non-compliant ACPI MADT tables - Address Kconfig warning * tag 'x86-urgent-2024-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu: Fix x86_match_cpu() to match just X86_VENDOR_INTEL crypto: x86/aes-xts - switch to new Intel CPU model defines x86/topology: Handle bogus ACPI tables correctly x86/kconfig: Select ARCH_WANT_FRAME_POINTERS again when UNWINDER_FRAME_POINTER=y
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‎arch/x86/Kconfig.debug‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -248,6 +248,7 @@ config UNWINDER_ORC
248248

249249
config UNWINDER_FRAME_POINTER
250250
bool "Frame pointer unwinder"
251+
select ARCH_WANT_FRAME_POINTERS
251252
select FRAME_POINTER
252253
help
253254
This option enables the frame pointer unwinder for unwinding kernel
@@ -271,7 +272,3 @@ config UNWINDER_GUESS
271272
overhead.
272273

273274
endchoice
274-
275-
config FRAME_POINTER
276-
depends on !UNWINDER_ORC && !UNWINDER_GUESS
277-
bool

‎arch/x86/crypto/aesni-intel_glue.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1223,14 +1223,14 @@ DEFINE_XTS_ALG(vaes_avx10_512, "xts-aes-vaes-avx10_512", 800);
12231223
* implementation with ymm registers (256-bit vectors) will be used instead.
12241224
*/
12251225
static const struct x86_cpu_id zmm_exclusion_list[] = {
1226-
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_SKYLAKE_X },
1227-
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_X },
1228-
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_D },
1229-
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE },
1230-
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_L },
1231-
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_NNPI },
1232-
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE_L },
1233-
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE },
1226+
X86_MATCH_VFM(INTEL_SKYLAKE_X, 0),
1227+
X86_MATCH_VFM(INTEL_ICELAKE_X, 0),
1228+
X86_MATCH_VFM(INTEL_ICELAKE_D, 0),
1229+
X86_MATCH_VFM(INTEL_ICELAKE, 0),
1230+
X86_MATCH_VFM(INTEL_ICELAKE_L, 0),
1231+
X86_MATCH_VFM(INTEL_ICELAKE_NNPI, 0),
1232+
X86_MATCH_VFM(INTEL_TIGERLAKE_L, 0),
1233+
X86_MATCH_VFM(INTEL_TIGERLAKE, 0),
12341234
/* Allow Rocket Lake and later, and Sapphire Rapids and later. */
12351235
/* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */
12361236
{},

‎arch/x86/include/asm/cpu_device_id.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,9 @@
5353
#define X86_CENTAUR_FAM6_C7_D 0xd
5454
#define X86_CENTAUR_FAM6_NANO 0xf
5555

56+
/* x86_cpu_id::flags */
57+
#define X86_CPU_ID_FLAG_ENTRY_VALID BIT(0)
58+
5659
#define X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins)
5760
/**
5861
* X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE - Base macro for CPU matching
@@ -79,6 +82,7 @@
7982
.model = _model, \
8083
.steppings = _steppings, \
8184
.feature = _feature, \
85+
.flags = X86_CPU_ID_FLAG_ENTRY_VALID, \
8286
.driver_data = (unsigned long) _data \
8387
}
8488

@@ -89,6 +93,7 @@
8993
.model = _model, \
9094
.steppings = _steppings, \
9195
.feature = _feature, \
96+
.flags = X86_CPU_ID_FLAG_ENTRY_VALID, \
9297
.driver_data = (unsigned long) _data \
9398
}
9499

‎arch/x86/kernel/cpu/match.c‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,7 @@ const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match)
3838
const struct x86_cpu_id *m;
3939
struct cpuinfo_x86 *c = &boot_cpu_data;
4040

41-
for (m = match;
42-
m->vendor | m->family | m->model | m->steppings | m->feature;
43-
m++) {
41+
for (m = match; m->flags & X86_CPU_ID_FLAG_ENTRY_VALID; m++) {
4442
if (m->vendor != X86_VENDOR_ANY && c->x86_vendor != m->vendor)
4543
continue;
4644
if (m->family != X86_FAMILY_ANY && c->x86 != m->family)

‎arch/x86/kernel/cpu/topology.c‎

Lines changed: 50 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,9 @@ static void topo_set_cpuids(unsigned int cpu, u32 apic_id, u32 acpi_id)
128128

129129
static __init bool check_for_real_bsp(u32 apic_id)
130130
{
131+
bool is_bsp = false, has_apic_base = boot_cpu_data.x86 >= 6;
132+
u64 msr;
133+
131134
/*
132135
* There is no real good way to detect whether this a kdump()
133136
* kernel, but except on the Voyager SMP monstrosity which is not
@@ -144,17 +147,61 @@ static __init bool check_for_real_bsp(u32 apic_id)
144147
if (topo_info.real_bsp_apic_id != BAD_APICID)
145148
return false;
146149

150+
/*
151+
* Check whether the enumeration order is broken by evaluating the
152+
* BSP bit in the APICBASE MSR. If the CPU does not have the
153+
* APICBASE MSR then the BSP detection is not possible and the
154+
* kernel must rely on the firmware enumeration order.
155+
*/
156+
if (has_apic_base) {
157+
rdmsrl(MSR_IA32_APICBASE, msr);
158+
is_bsp = !!(msr & MSR_IA32_APICBASE_BSP);
159+
}
160+
147161
if (apic_id == topo_info.boot_cpu_apic_id) {
148-
topo_info.real_bsp_apic_id = apic_id;
149-
return false;
162+
/*
163+
* If the boot CPU has the APIC BSP bit set then the
164+
* firmware enumeration is agreeing. If the CPU does not
165+
* have the APICBASE MSR then the only choice is to trust
166+
* the enumeration order.
167+
*/
168+
if (is_bsp || !has_apic_base) {
169+
topo_info.real_bsp_apic_id = apic_id;
170+
return false;
171+
}
172+
/*
173+
* If the boot APIC is enumerated first, but the APICBASE
174+
* MSR does not have the BSP bit set, then there is no way
175+
* to discover the real BSP here. Assume a crash kernel and
176+
* limit the number of CPUs to 1 as an INIT to the real BSP
177+
* would reset the machine.
178+
*/
179+
pr_warn("Enumerated BSP APIC %x is not marked in APICBASE MSR\n", apic_id);
180+
pr_warn("Assuming crash kernel. Limiting to one CPU to prevent machine INIT\n");
181+
set_nr_cpu_ids(1);
182+
goto fwbug;
150183
}
151184

152-
pr_warn("Boot CPU APIC ID not the first enumerated APIC ID: %x > %x\n",
185+
pr_warn("Boot CPU APIC ID not the first enumerated APIC ID: %x != %x\n",
153186
topo_info.boot_cpu_apic_id, apic_id);
187+
188+
if (is_bsp) {
189+
/*
190+
* The boot CPU has the APIC BSP bit set. Use it and complain
191+
* about the broken firmware enumeration.
192+
*/
193+
topo_info.real_bsp_apic_id = topo_info.boot_cpu_apic_id;
194+
goto fwbug;
195+
}
196+
154197
pr_warn("Crash kernel detected. Disabling real BSP to prevent machine INIT\n");
155198

156199
topo_info.real_bsp_apic_id = apic_id;
157200
return true;
201+
202+
fwbug:
203+
pr_warn(FW_BUG "APIC enumeration order not specification compliant\n");
204+
return false;
158205
}
159206

160207
static unsigned int topo_unit_count(u32 lvlid, enum x86_topology_domains at_level,

‎include/linux/mod_devicetable.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -690,6 +690,8 @@ struct x86_cpu_id {
690690
__u16 model;
691691
__u16 steppings;
692692
__u16 feature; /* bit index */
693+
/* Solely for kernel-internal use: DO NOT EXPORT to userspace! */
694+
__u16 flags;
693695
kernel_ulong_t driver_data;
694696
};
695697

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