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107 | 107 | #define RGS_HDMITX_5T1_EDG (0xf << 4)
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108 | 108 | #define RGS_HDMITX_PLUG_TST BIT(0)
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109 | 109 |
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110 |
| -static const u8 PREDIV[3][4] = { |
111 |
| - {0x0, 0x0, 0x0, 0x0}, /* 27Mhz */ |
112 |
| - {0x1, 0x1, 0x1, 0x1}, /* 74Mhz */ |
113 |
| - {0x1, 0x1, 0x1, 0x1} /* 148Mhz */ |
114 |
| -}; |
115 |
| - |
116 |
| -static const u8 TXDIV[3][4] = { |
117 |
| - {0x3, 0x3, 0x3, 0x2}, /* 27Mhz */ |
118 |
| - {0x2, 0x1, 0x1, 0x1}, /* 74Mhz */ |
119 |
| - {0x1, 0x0, 0x0, 0x0} /* 148Mhz */ |
120 |
| -}; |
121 |
| - |
122 |
| -static const u8 FBKSEL[3][4] = { |
123 |
| - {0x1, 0x1, 0x1, 0x1}, /* 27Mhz */ |
124 |
| - {0x1, 0x0, 0x1, 0x1}, /* 74Mhz */ |
125 |
| - {0x1, 0x0, 0x1, 0x1} /* 148Mhz */ |
126 |
| -}; |
127 |
| - |
128 |
| -static const u8 FBKDIV[3][4] = { |
129 |
| - {19, 24, 29, 19}, /* 27Mhz */ |
130 |
| - {19, 24, 14, 19}, /* 74Mhz */ |
131 |
| - {19, 24, 14, 19} /* 148Mhz */ |
132 |
| -}; |
133 |
| - |
134 |
| -static const u8 DIVEN[3][4] = { |
135 |
| - {0x2, 0x1, 0x1, 0x2}, /* 27Mhz */ |
136 |
| - {0x2, 0x2, 0x2, 0x2}, /* 74Mhz */ |
137 |
| - {0x2, 0x2, 0x2, 0x2} /* 148Mhz */ |
138 |
| -}; |
139 |
| - |
140 |
| -static const u8 HTPLLBP[3][4] = { |
141 |
| - {0xc, 0xc, 0x8, 0xc}, /* 27Mhz */ |
142 |
| - {0xc, 0xf, 0xf, 0xc}, /* 74Mhz */ |
143 |
| - {0xc, 0xf, 0xf, 0xc} /* 148Mhz */ |
144 |
| -}; |
145 |
| - |
146 |
| -static const u8 HTPLLBC[3][4] = { |
147 |
| - {0x2, 0x3, 0x3, 0x2}, /* 27Mhz */ |
148 |
| - {0x2, 0x3, 0x3, 0x2}, /* 74Mhz */ |
149 |
| - {0x2, 0x3, 0x3, 0x2} /* 148Mhz */ |
150 |
| -}; |
151 |
| - |
152 |
| -static const u8 HTPLLBR[3][4] = { |
153 |
| - {0x1, 0x1, 0x0, 0x1}, /* 27Mhz */ |
154 |
| - {0x1, 0x2, 0x2, 0x1}, /* 74Mhz */ |
155 |
| - {0x1, 0x2, 0x2, 0x1} /* 148Mhz */ |
156 |
| -}; |
157 |
| - |
158 | 110 | static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
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159 | 111 | {
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160 | 112 | struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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