riscv: poison SBI calls for M-mode

Christoph Hellwig · paul-walmsley-sifive · commit 3b03ac6bbd6e · 2019-11-13T13:20:41.000-08:00
There is no SBI when we run in M-mode, so fail the compile for any code
trying to use SBI calls.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+#ifdef CONFIG_RISCV_SBI
 #define SBI_SET_TIMER 0
 #define SBI_CONSOLE_PUTCHAR 1
 #define SBI_CONSOLE_GETCHAR 2
@@ -93,5 +94,5 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
 {
 	SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
 }
-
-#endif
+#endif /* CONFIG_RISCV_SBI */
+#endif /* _ASM_RISCV_SBI_H */

Original file line number	Diff line number	Diff line change
`@@ -8,6 +8,7 @@`
`8`	`8`
`9`	`9`	`#include <linux/types.h>`
`10`	`10`
	`11`	`+#ifdef CONFIG_RISCV_SBI`
`11`	`12`	`#define SBI_SET_TIMER 0`
`12`	`13`	`#define SBI_CONSOLE_PUTCHAR 1`
`13`	`14`	`#define SBI_CONSOLE_GETCHAR 2`
`@@ -93,5 +94,5 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,`
`93`	`94`	`{`
`94`	`95`	`SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);`
`95`	`96`	`}`
`96`		`-`
`97`		`-#endif`
	`97`	`+#endif /* CONFIG_RISCV_SBI */`
	`98`	`+#endif /* _ASM_RISCV_SBI_H */`