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torvaldstorvalds
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Merge tag 'pinctrl-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij: "Here is a bunch of pin control fixes. I was lagging behind on this one, some fixes should have come in earlier, sorry about that. Anyways here it is, pretty straight-forward fixes, the Strago fix stand out as something serious affecting a lot of machines. Summary: - Handle multiple instances of Intel chips without complaining. - Restore the Intel Strago DMI workaround - Make the Armada 37xx handle pins over 32 - Fix the polarity of the LED group on Armada 37xx - Fix an off-by-one bug in the NS2 driver - Fix error path for iproc's platform_get_irq() - Fix error path on the STMFX driver - Fix a typo in the Berlin AS370 driver - Fix up misc errors in the Aspeed 2600 BMC support - Fix a stray SPDX tag" * tag 'pinctrl-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups pinctrl: aspeed-g6: Fix UART13 group pinmux pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration pinctrl: aspeed-g6: Fix I2C14 SDA description pinctrl: aspeed-g6: Sort pins for sanity dt-bindings: pinctrl: aspeed-g6: Rework SD3 function and groups pinctrl: berlin: as370: fix a typo s/spififib/spdifib pinctrl: armada-37xx: swap polarity on LED group pinctrl: stmfx: fix null pointer on remove pinctrl: iproc: allow for error from platform_get_irq() pinctrl: ns2: Fix off by one bugs in ns2_pinmux_enable() pinctrl: bcm-iproc: Use SPDX header pinctrl: armada-37xx: fix control of pins 32 and up pinctrl: cherryview: restore Strago DMI workaround for all versions pinctrl: intel: Allocate IRQ chip dynamic
2 parents 7d194c2 + d6e7a1a commit 3b7c59a

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‎Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml

Lines changed: 42 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -33,13 +33,13 @@ patternProperties:
3333
allOf:
3434
- $ref: "/schemas/types.yaml#/definitions/string"
3535
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
36-
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
37-
ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1,
38-
GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2,
39-
GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12,
40-
I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7,
41-
I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC,
42-
LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
36+
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC,
37+
ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0,
38+
GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
39+
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11,
40+
I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6,
41+
I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
42+
LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
4343
MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2,
4444
NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
4545
NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
@@ -48,47 +48,45 @@ patternProperties:
4848
PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
4949
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12,
5050
SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5,
51-
SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5,
52-
SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO,
53-
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1,
54-
SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
55-
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5,
56-
TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1,
57-
TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7,
58-
UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
59-
WDTRST4, ]
51+
SALT6, SALT7, SALT8, SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL,
52+
SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
53+
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
54+
TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
55+
TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
56+
THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
57+
UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
58+
WDTRST3, WDTRST4, ]
6059
groups:
6160
allOf:
6261
- $ref: "/schemas/types.yaml#/definitions/string"
6362
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
64-
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
65-
ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0,
66-
GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
67-
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1,
68-
I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3,
69-
I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6,
70-
JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
71-
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3,
72-
MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
73-
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1,
74-
NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE,
75-
PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1,
76-
PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3,
77-
PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
78-
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
79-
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1,
80-
SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1,
81-
SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1,
82-
SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0,
83-
SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7,
84-
SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD,
85-
SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
86-
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13,
87-
TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8,
88-
TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4,
89-
UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
90-
UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
91-
WDTRST4, ]
63+
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1,
64+
EMMCG4, EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID,
65+
FWQSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5,
66+
GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6,
67+
GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14,
68+
I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9,
69+
I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD,
70+
LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4,
71+
MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1,
72+
NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
73+
NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
74+
OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1,
75+
PWM12G0, PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0,
76+
PWM15G1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1,
77+
PWM9G0, PWM9G1, QSPI1, QSPI2, RGMII1, RGMII2, RGMII3, RGMII4,
78+
RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1,
79+
SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1,
80+
SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1,
81+
SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7,
82+
SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL,
83+
SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
84+
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
85+
TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
86+
TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
87+
THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
88+
UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,
89+
VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]
9290

9391
required:
9492
- compatible

‎drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

Lines changed: 54 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ FUNC_GROUP_DECL(MACLINK3, L23);
8787

8888
#define K25 7
8989
SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7));
90-
SIG_EXPR_LIST_DECL_SESG(K25, SDA14, SDA14, SIG_DESC_SET(SCU4B0, 7));
90+
SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7));
9191
PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14);
9292
FUNC_GROUP_DECL(MACLINK4, K25);
9393

@@ -1262,13 +1262,13 @@ GROUP_DECL(SPI1, AB11, AC11, AA11);
12621262
#define AD11 206
12631263
SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14));
12641264
SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13,
1265-
SIG_DESC_SET(SCU438, 14));
1265+
SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14));
12661266
PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13);
12671267

12681268
#define AF10 207
12691269
SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15));
12701270
SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13,
1271-
SIG_DESC_SET(SCU438, 15));
1271+
SIG_DESC_CLEAR(SCU4B8, 3), SIG_DESC_SET(SCU4D8, 15));
12721272
PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13);
12731273

12741274
GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10);
@@ -1440,91 +1440,85 @@ FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
14401440
FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
14411441

14421442
#define AB4 232
1443-
SIG_EXPR_LIST_DECL_SESG(AB4, SD3CLK, SD3, SIG_DESC_SET(SCU400, 24));
1444-
PIN_DECL_1(AB4, GPIO18D0, SD3CLK);
1443+
SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24));
1444+
PIN_DECL_1(AB4, GPIO18D0, EMMCCLK);
14451445

14461446
#define AA4 233
1447-
SIG_EXPR_LIST_DECL_SESG(AA4, SD3CMD, SD3, SIG_DESC_SET(SCU400, 25));
1448-
PIN_DECL_1(AA4, GPIO18D1, SD3CMD);
1447+
SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25));
1448+
PIN_DECL_1(AA4, GPIO18D1, EMMCCMD);
14491449

14501450
#define AC4 234
1451-
SIG_EXPR_LIST_DECL_SESG(AC4, SD3DAT0, SD3, SIG_DESC_SET(SCU400, 26));
1452-
PIN_DECL_1(AC4, GPIO18D2, SD3DAT0);
1451+
SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26));
1452+
PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0);
14531453

14541454
#define AA5 235
1455-
SIG_EXPR_LIST_DECL_SESG(AA5, SD3DAT1, SD3, SIG_DESC_SET(SCU400, 27));
1456-
PIN_DECL_1(AA5, GPIO18D3, SD3DAT1);
1455+
SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27));
1456+
PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1);
14571457

14581458
#define Y5 236
1459-
SIG_EXPR_LIST_DECL_SESG(Y5, SD3DAT2, SD3, SIG_DESC_SET(SCU400, 28));
1460-
PIN_DECL_1(Y5, GPIO18D4, SD3DAT2);
1459+
SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28));
1460+
PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2);
14611461

14621462
#define AB5 237
1463-
SIG_EXPR_LIST_DECL_SESG(AB5, SD3DAT3, SD3, SIG_DESC_SET(SCU400, 29));
1464-
PIN_DECL_1(AB5, GPIO18D5, SD3DAT3);
1463+
SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29));
1464+
PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3);
14651465

14661466
#define AB6 238
1467-
SIG_EXPR_LIST_DECL_SESG(AB6, SD3CD, SD3, SIG_DESC_SET(SCU400, 30));
1468-
PIN_DECL_1(AB6, GPIO18D6, SD3CD);
1467+
SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30));
1468+
PIN_DECL_1(AB6, GPIO18D6, EMMCCD);
14691469

14701470
#define AC5 239
1471-
SIG_EXPR_LIST_DECL_SESG(AC5, SD3WP, SD3, SIG_DESC_SET(SCU400, 31));
1472-
PIN_DECL_1(AC5, GPIO18D7, SD3WP);
1471+
SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31));
1472+
PIN_DECL_1(AC5, GPIO18D7, EMMCWP);
14731473

1474-
FUNC_GROUP_DECL(SD3, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5);
1474+
GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5);
1475+
GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5);
14751476

14761477
#define Y1 240
14771478
SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
14781479
SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5));
1479-
SIG_EXPR_LIST_DECL_SESG(Y1, SD3DAT4, SD3DAT4, SIG_DESC_SET(SCU404, 0));
1480-
PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, SD3DAT4);
1481-
FUNC_GROUP_DECL(SD3DAT4, Y1);
1480+
SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0));
1481+
PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4);
14821482

14831483
#define Y2 241
14841484
SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
14851485
SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5));
1486-
SIG_EXPR_LIST_DECL_SESG(Y2, SD3DAT5, SD3DAT5, SIG_DESC_SET(SCU404, 1));
1487-
PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, SD3DAT5);
1488-
FUNC_GROUP_DECL(SD3DAT5, Y2);
1486+
SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1));
1487+
PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5);
14891488

14901489
#define Y3 242
14911490
SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID,
14921491
SIG_DESC_SET(SCU500, 3));
14931492
SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5));
1494-
SIG_EXPR_LIST_DECL_SESG(Y3, SD3DAT6, SD3DAT6, SIG_DESC_SET(SCU404, 2));
1495-
PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, SD3DAT6);
1496-
FUNC_GROUP_DECL(SD3DAT6, Y3);
1493+
SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2));
1494+
PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6);
14971495

14981496
#define Y4 243
14991497
SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID,
15001498
SIG_DESC_SET(SCU500, 3));
15011499
SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5));
1502-
SIG_EXPR_LIST_DECL_SESG(Y4, SD3DAT7, SD3DAT7, SIG_DESC_SET(SCU404, 3));
1503-
PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, SD3DAT7);
1504-
FUNC_GROUP_DECL(SD3DAT7, Y4);
1500+
SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3));
1501+
PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7);
15051502

15061503
GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4);
15071504
GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12);
1505+
GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4);
15081506
FUNC_DECL_2(FWSPID, FWSPID, FWQSPID);
15091507
FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4);
1510-
1508+
FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8);
15111509
/*
15121510
* FIXME: Confirm bits and priorities are the right way around for the
15131511
* following 4 pins
15141512
*/
15151513
#define AF25 244
1516-
SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20),
1517-
SIG_DESC_SET(SCU4D8, 20));
1518-
SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_CLEAR(SCU438, 20),
1519-
SIG_DESC_SET(SCU4D8, 20));
1514+
SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20));
1515+
SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20));
15201516
PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL),
15211517
SIG_EXPR_LIST_PTR(AF25, FSI1CLK));
15221518

15231519
#define AE26 245
1524-
SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21),
1525-
SIG_DESC_SET(SCU4D8, 21));
1526-
SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_CLEAR(SCU438, 21),
1527-
SIG_DESC_SET(SCU4D8, 21));
1520+
SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21));
1521+
SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21));
15281522
PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA),
15291523
SIG_EXPR_LIST_PTR(AE26, FSI1DATA));
15301524

@@ -1533,18 +1527,14 @@ FUNC_DECL_2(I3C3, HVI3C3, I3C3);
15331527
FUNC_GROUP_DECL(FSI1, AF25, AE26);
15341528

15351529
#define AE25 246
1536-
SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22),
1537-
SIG_DESC_SET(SCU4D8, 22));
1538-
SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_CLEAR(SCU438, 22),
1539-
SIG_DESC_SET(SCU4D8, 22));
1530+
SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22));
1531+
SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22));
15401532
PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL),
15411533
SIG_EXPR_LIST_PTR(AE25, FSI2CLK));
15421534

15431535
#define AF24 247
1544-
SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23),
1545-
SIG_DESC_SET(SCU4D8, 23));
1546-
SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_CLEAR(SCU438, 23),
1547-
SIG_DESC_SET(SCU4D8, 23));
1536+
SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23));
1537+
SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23));
15481538
PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA),
15491539
SIG_EXPR_LIST_PTR(AF24, FSI2DATA));
15501540

@@ -1574,6 +1564,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
15741564
ASPEED_PINCTRL_PIN(A3),
15751565
ASPEED_PINCTRL_PIN(AA11),
15761566
ASPEED_PINCTRL_PIN(AA12),
1567+
ASPEED_PINCTRL_PIN(AA16),
1568+
ASPEED_PINCTRL_PIN(AA17),
15771569
ASPEED_PINCTRL_PIN(AA23),
15781570
ASPEED_PINCTRL_PIN(AA24),
15791571
ASPEED_PINCTRL_PIN(AA25),
@@ -1585,6 +1577,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
15851577
ASPEED_PINCTRL_PIN(AB11),
15861578
ASPEED_PINCTRL_PIN(AB12),
15871579
ASPEED_PINCTRL_PIN(AB15),
1580+
ASPEED_PINCTRL_PIN(AB16),
1581+
ASPEED_PINCTRL_PIN(AB17),
15881582
ASPEED_PINCTRL_PIN(AB18),
15891583
ASPEED_PINCTRL_PIN(AB19),
15901584
ASPEED_PINCTRL_PIN(AB22),
@@ -1602,6 +1596,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
16021596
ASPEED_PINCTRL_PIN(AC11),
16031597
ASPEED_PINCTRL_PIN(AC12),
16041598
ASPEED_PINCTRL_PIN(AC15),
1599+
ASPEED_PINCTRL_PIN(AC16),
16051600
ASPEED_PINCTRL_PIN(AC17),
16061601
ASPEED_PINCTRL_PIN(AC18),
16071602
ASPEED_PINCTRL_PIN(AC19),
@@ -1619,6 +1614,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
16191614
ASPEED_PINCTRL_PIN(AD12),
16201615
ASPEED_PINCTRL_PIN(AD14),
16211616
ASPEED_PINCTRL_PIN(AD15),
1617+
ASPEED_PINCTRL_PIN(AD16),
16221618
ASPEED_PINCTRL_PIN(AD19),
16231619
ASPEED_PINCTRL_PIN(AD20),
16241620
ASPEED_PINCTRL_PIN(AD22),
@@ -1634,15 +1630,20 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
16341630
ASPEED_PINCTRL_PIN(AE12),
16351631
ASPEED_PINCTRL_PIN(AE14),
16361632
ASPEED_PINCTRL_PIN(AE15),
1633+
ASPEED_PINCTRL_PIN(AE16),
16371634
ASPEED_PINCTRL_PIN(AE18),
16381635
ASPEED_PINCTRL_PIN(AE19),
1636+
ASPEED_PINCTRL_PIN(AE25),
1637+
ASPEED_PINCTRL_PIN(AE26),
16391638
ASPEED_PINCTRL_PIN(AE7),
16401639
ASPEED_PINCTRL_PIN(AE8),
16411640
ASPEED_PINCTRL_PIN(AF10),
16421641
ASPEED_PINCTRL_PIN(AF11),
16431642
ASPEED_PINCTRL_PIN(AF12),
16441643
ASPEED_PINCTRL_PIN(AF14),
16451644
ASPEED_PINCTRL_PIN(AF15),
1645+
ASPEED_PINCTRL_PIN(AF24),
1646+
ASPEED_PINCTRL_PIN(AF25),
16461647
ASPEED_PINCTRL_PIN(AF7),
16471648
ASPEED_PINCTRL_PIN(AF8),
16481649
ASPEED_PINCTRL_PIN(AF9),
@@ -1792,17 +1793,6 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
17921793
ASPEED_PINCTRL_PIN(Y3),
17931794
ASPEED_PINCTRL_PIN(Y4),
17941795
ASPEED_PINCTRL_PIN(Y5),
1795-
ASPEED_PINCTRL_PIN(AB16),
1796-
ASPEED_PINCTRL_PIN(AA17),
1797-
ASPEED_PINCTRL_PIN(AB17),
1798-
ASPEED_PINCTRL_PIN(AE16),
1799-
ASPEED_PINCTRL_PIN(AC16),
1800-
ASPEED_PINCTRL_PIN(AA16),
1801-
ASPEED_PINCTRL_PIN(AD16),
1802-
ASPEED_PINCTRL_PIN(AF25),
1803-
ASPEED_PINCTRL_PIN(AE26),
1804-
ASPEED_PINCTRL_PIN(AE25),
1805-
ASPEED_PINCTRL_PIN(AF24),
18061796
};
18071797

18081798
static const struct aspeed_pin_group aspeed_g6_groups[] = {
@@ -1976,11 +1966,9 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = {
19761966
ASPEED_PINCTRL_GROUP(SALT9G1),
19771967
ASPEED_PINCTRL_GROUP(SD1),
19781968
ASPEED_PINCTRL_GROUP(SD2),
1979-
ASPEED_PINCTRL_GROUP(SD3),
1980-
ASPEED_PINCTRL_GROUP(SD3DAT4),
1981-
ASPEED_PINCTRL_GROUP(SD3DAT5),
1982-
ASPEED_PINCTRL_GROUP(SD3DAT6),
1983-
ASPEED_PINCTRL_GROUP(SD3DAT7),
1969+
ASPEED_PINCTRL_GROUP(EMMCG1),
1970+
ASPEED_PINCTRL_GROUP(EMMCG4),
1971+
ASPEED_PINCTRL_GROUP(EMMCG8),
19841972
ASPEED_PINCTRL_GROUP(SGPM1),
19851973
ASPEED_PINCTRL_GROUP(SGPS1),
19861974
ASPEED_PINCTRL_GROUP(SIOONCTRL),
@@ -2059,6 +2047,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
20592047
ASPEED_PINCTRL_FUNC(ADC8),
20602048
ASPEED_PINCTRL_FUNC(ADC9),
20612049
ASPEED_PINCTRL_FUNC(BMCINT),
2050+
ASPEED_PINCTRL_FUNC(EMMC),
20622051
ASPEED_PINCTRL_FUNC(ESPI),
20632052
ASPEED_PINCTRL_FUNC(ESPIALT),
20642053
ASPEED_PINCTRL_FUNC(FSI1),
@@ -2191,11 +2180,6 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
21912180
ASPEED_PINCTRL_FUNC(SALT9),
21922181
ASPEED_PINCTRL_FUNC(SD1),
21932182
ASPEED_PINCTRL_FUNC(SD2),
2194-
ASPEED_PINCTRL_FUNC(SD3),
2195-
ASPEED_PINCTRL_FUNC(SD3DAT4),
2196-
ASPEED_PINCTRL_FUNC(SD3DAT5),
2197-
ASPEED_PINCTRL_FUNC(SD3DAT6),
2198-
ASPEED_PINCTRL_FUNC(SD3DAT7),
21992183
ASPEED_PINCTRL_FUNC(SGPM1),
22002184
ASPEED_PINCTRL_FUNC(SGPS1),
22012185
ASPEED_PINCTRL_FUNC(SIOONCTRL),

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