We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 90b593c commit 3bf8466Copy full SHA for 3bf8466
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -39,8 +39,8 @@ struct a6xx_gpu {
39
40
/*
41
* Given a register and a count, return a value to program into
42
- * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
43
- * registers starting at _reg.
+ * REG_CP_PROTECT_REG(n) - this will block both reads and writes for
+ * _len + 1 registers starting at _reg.
44
*/
45
#define A6XX_PROTECT_NORDWR(_reg, _len) \
46
((1 << 31) | \
0 commit comments