@@ -352,26 +352,26 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
352
352
cxdbg = ioremap (res -> start , resource_size (res ));
353
353
354
354
if (cxdbg ) {
355
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_CNTLT ,
355
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT ,
356
356
A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT (0xf ));
357
357
358
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_CNTLM ,
358
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM ,
359
359
A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE (0xf ));
360
360
361
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 , 0 );
362
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 , 0 );
363
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 , 0 );
364
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 , 0 );
361
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 , 0 );
362
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 , 0 );
363
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 , 0 );
364
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 , 0 );
365
365
366
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 ,
366
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 ,
367
367
0x76543210 );
368
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 ,
368
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 ,
369
369
0xFEDCBA98 );
370
370
371
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 , 0 );
372
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 , 0 );
373
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 , 0 );
374
- cxdbg_write (cxdbg , REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 , 0 );
371
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 , 0 );
372
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 , 0 );
373
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 , 0 );
374
+ cxdbg_write (cxdbg , REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 , 0 );
375
375
}
376
376
377
377
a6xx_state -> debugbus = state_kcalloc (a6xx_state ,
0 commit comments