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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
| 2 | + |
| 3 | +/* This include file covers the common peripherals and configuration between |
| 4 | + * bcm2835, bcm2836 and bcm2837 implementations. |
| 5 | + */ |
| 6 | + |
| 7 | +/ { |
| 8 | + interrupt-parent = <&intc>; |
| 9 | + |
| 10 | + soc { |
| 11 | + dma: dma@7e007000 { |
| 12 | + compatible = "brcm,bcm2835-dma"; |
| 13 | + reg = <0x7e007000 0xf00>; |
| 14 | + interrupts = <1 16>, |
| 15 | + <1 17>, |
| 16 | + <1 18>, |
| 17 | + <1 19>, |
| 18 | + <1 20>, |
| 19 | + <1 21>, |
| 20 | + <1 22>, |
| 21 | + <1 23>, |
| 22 | + <1 24>, |
| 23 | + <1 25>, |
| 24 | + <1 26>, |
| 25 | + /* dma channel 11-14 share one irq */ |
| 26 | + <1 27>, |
| 27 | + <1 27>, |
| 28 | + <1 27>, |
| 29 | + <1 27>, |
| 30 | + /* unused shared irq for all channels */ |
| 31 | + <1 28>; |
| 32 | + interrupt-names = "dma0", |
| 33 | + "dma1", |
| 34 | + "dma2", |
| 35 | + "dma3", |
| 36 | + "dma4", |
| 37 | + "dma5", |
| 38 | + "dma6", |
| 39 | + "dma7", |
| 40 | + "dma8", |
| 41 | + "dma9", |
| 42 | + "dma10", |
| 43 | + "dma11", |
| 44 | + "dma12", |
| 45 | + "dma13", |
| 46 | + "dma14", |
| 47 | + "dma-shared-all"; |
| 48 | + #dma-cells = <1>; |
| 49 | + brcm,dma-channel-mask = <0x7f35>; |
| 50 | + }; |
| 51 | + |
| 52 | + intc: interrupt-controller@7e00b200 { |
| 53 | + compatible = "brcm,bcm2835-armctrl-ic"; |
| 54 | + reg = <0x7e00b200 0x200>; |
| 55 | + interrupt-controller; |
| 56 | + #interrupt-cells = <2>; |
| 57 | + }; |
| 58 | + |
| 59 | + pm: watchdog@7e100000 { |
| 60 | + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; |
| 61 | + #power-domain-cells = <1>; |
| 62 | + #reset-cells = <1>; |
| 63 | + reg = <0x7e100000 0x114>, |
| 64 | + <0x7e00a000 0x24>; |
| 65 | + clocks = <&clocks BCM2835_CLOCK_V3D>, |
| 66 | + <&clocks BCM2835_CLOCK_PERI_IMAGE>, |
| 67 | + <&clocks BCM2835_CLOCK_H264>, |
| 68 | + <&clocks BCM2835_CLOCK_ISP>; |
| 69 | + clock-names = "v3d", "peri_image", "h264", "isp"; |
| 70 | + system-power-controller; |
| 71 | + }; |
| 72 | + |
| 73 | + pixelvalve@7e206000 { |
| 74 | + compatible = "brcm,bcm2835-pixelvalve0"; |
| 75 | + reg = <0x7e206000 0x100>; |
| 76 | + interrupts = <2 13>; /* pwa0 */ |
| 77 | + }; |
| 78 | + |
| 79 | + pixelvalve@7e207000 { |
| 80 | + compatible = "brcm,bcm2835-pixelvalve1"; |
| 81 | + reg = <0x7e207000 0x100>; |
| 82 | + interrupts = <2 14>; /* pwa1 */ |
| 83 | + }; |
| 84 | + |
| 85 | + thermal: thermal@7e212000 { |
| 86 | + compatible = "brcm,bcm2835-thermal"; |
| 87 | + reg = <0x7e212000 0x8>; |
| 88 | + clocks = <&clocks BCM2835_CLOCK_TSENS>; |
| 89 | + #thermal-sensor-cells = <0>; |
| 90 | + status = "disabled"; |
| 91 | + }; |
| 92 | + |
| 93 | + i2c2: i2c@7e805000 { |
| 94 | + compatible = "brcm,bcm2835-i2c"; |
| 95 | + reg = <0x7e805000 0x1000>; |
| 96 | + interrupts = <2 21>; |
| 97 | + clocks = <&clocks BCM2835_CLOCK_VPU>; |
| 98 | + #address-cells = <1>; |
| 99 | + #size-cells = <0>; |
| 100 | + status = "okay"; |
| 101 | + }; |
| 102 | + |
| 103 | + pixelvalve@7e807000 { |
| 104 | + compatible = "brcm,bcm2835-pixelvalve2"; |
| 105 | + reg = <0x7e807000 0x100>; |
| 106 | + interrupts = <2 10>; /* pixelvalve */ |
| 107 | + }; |
| 108 | + |
| 109 | + hdmi: hdmi@7e902000 { |
| 110 | + compatible = "brcm,bcm2835-hdmi"; |
| 111 | + reg = <0x7e902000 0x600>, |
| 112 | + <0x7e808000 0x100>; |
| 113 | + interrupts = <2 8>, <2 9>; |
| 114 | + ddc = <&i2c2>; |
| 115 | + clocks = <&clocks BCM2835_PLLH_PIX>, |
| 116 | + <&clocks BCM2835_CLOCK_HSM>; |
| 117 | + clock-names = "pixel", "hdmi"; |
| 118 | + dmas = <&dma 17>; |
| 119 | + dma-names = "audio-rx"; |
| 120 | + status = "disabled"; |
| 121 | + }; |
| 122 | + |
| 123 | + v3d: v3d@7ec00000 { |
| 124 | + compatible = "brcm,bcm2835-v3d"; |
| 125 | + reg = <0x7ec00000 0x1000>; |
| 126 | + interrupts = <1 10>; |
| 127 | + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; |
| 128 | + }; |
| 129 | + |
| 130 | + vc4: gpu { |
| 131 | + compatible = "brcm,bcm2835-vc4"; |
| 132 | + }; |
| 133 | + }; |
| 134 | +}; |
| 135 | + |
| 136 | +&cpu_thermal { |
| 137 | + thermal-sensors = <&thermal>; |
| 138 | +}; |
| 139 | + |
| 140 | +&gpio { |
| 141 | + i2c_slave_gpio18: i2c_slave_gpio18 { |
| 142 | + brcm,pins = <18 19 20 21>; |
| 143 | + brcm,function = <BCM2835_FSEL_ALT3>; |
| 144 | + }; |
| 145 | + |
| 146 | + jtag_gpio4: jtag_gpio4 { |
| 147 | + brcm,pins = <4 5 6 12 13>; |
| 148 | + brcm,function = <BCM2835_FSEL_ALT5>; |
| 149 | + }; |
| 150 | + |
| 151 | + pwm0_gpio12: pwm0_gpio12 { |
| 152 | + brcm,pins = <12>; |
| 153 | + brcm,function = <BCM2835_FSEL_ALT0>; |
| 154 | + }; |
| 155 | + pwm0_gpio18: pwm0_gpio18 { |
| 156 | + brcm,pins = <18>; |
| 157 | + brcm,function = <BCM2835_FSEL_ALT5>; |
| 158 | + }; |
| 159 | + pwm0_gpio40: pwm0_gpio40 { |
| 160 | + brcm,pins = <40>; |
| 161 | + brcm,function = <BCM2835_FSEL_ALT0>; |
| 162 | + }; |
| 163 | + pwm1_gpio13: pwm1_gpio13 { |
| 164 | + brcm,pins = <13>; |
| 165 | + brcm,function = <BCM2835_FSEL_ALT0>; |
| 166 | + }; |
| 167 | + pwm1_gpio19: pwm1_gpio19 { |
| 168 | + brcm,pins = <19>; |
| 169 | + brcm,function = <BCM2835_FSEL_ALT5>; |
| 170 | + }; |
| 171 | + pwm1_gpio41: pwm1_gpio41 { |
| 172 | + brcm,pins = <41>; |
| 173 | + brcm,function = <BCM2835_FSEL_ALT0>; |
| 174 | + }; |
| 175 | + pwm1_gpio45: pwm1_gpio45 { |
| 176 | + brcm,pins = <45>; |
| 177 | + brcm,function = <BCM2835_FSEL_ALT0>; |
| 178 | + }; |
| 179 | +}; |
| 180 | + |
| 181 | +&i2s { |
| 182 | + dmas = <&dma 2>, <&dma 3>; |
| 183 | + dma-names = "tx", "rx"; |
| 184 | +}; |
| 185 | + |
| 186 | +&sdhost { |
| 187 | + dmas = <&dma 13>; |
| 188 | + dma-names = "rx-tx"; |
| 189 | +}; |
| 190 | + |
| 191 | +&spi { |
| 192 | + dmas = <&dma 6>, <&dma 7>; |
| 193 | + dma-names = "tx", "rx"; |
| 194 | +}; |
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