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pinctrl: renesas: r8a779g0: Fix (H)SCIF1 suffixes
The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series Hardware User's Manual still has two alternate pin groups (GP0_14-18 and GP1_6-10) each named both HSCIF1 and SCIF1. To differentiate, the pin control driver uses "(h)scif1" and "(h)scif1_x", which were considered temporary names until the conflict was sorted out. Fix this by adopting R-Car V4M naming: - Rename "(h)scif1" to "(h)scif1_a", - Rename "(h)scif1_x" to "(h)scif1_b". Adopt the R-Car V4M naming "(h)scif1_a" and "(h)scif1_b" to increase uniformity. While at it, remove unneeded separators. Fixes: ad9bb2f ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442a ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: cf4f789 ("pinctrl: renesas: r8a779g0: Add missing HSCIF1_X") Fixes: 9c151c2 ("pinctrl: renesas: r8a779g0: Add missing SCIF1_X") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/5009130d1867e12abf9b231c8838fd05e2b28bee.1717754960.git.geert+renesas@glider.be
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‎drivers/pinctrl/renesas/pfc-r8a779g0.c

Lines changed: 102 additions & 106 deletions
Original file line numberDiff line numberDiff line change
@@ -291,13 +291,13 @@
291291
#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292292
#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293293
#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294-
#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295-
#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294+
#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295+
#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296296

297297
/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
298-
#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299-
#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300-
#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298+
#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299+
#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300+
#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301301

302302
/* SR1 */
303303
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -307,13 +307,13 @@
307307
#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308308
#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309309
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310-
#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311-
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310+
#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311+
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312312

313313
/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
314-
#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315-
#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316-
#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314+
#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315+
#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316+
#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317317
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318318
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319319
#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -754,25 +754,25 @@ static const u16 pinmux_data[] = {
754754
PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A),
755755

756756
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
757-
PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1),
758-
PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1),
757+
PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),
758+
PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),
759759

760760
PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
761-
PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1),
762-
PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1),
761+
PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A),
762+
PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A),
763763

764764
/* IP2SR0 */
765765
PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
766-
PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N),
767-
PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N),
766+
PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A),
767+
PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A),
768768

769769
PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
770-
PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N),
771-
PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N),
770+
PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A),
771+
PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A),
772772

773773
PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
774-
PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1),
775-
PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1),
774+
PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A),
775+
PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A),
776776

777777
/* IP0SR1 */
778778
PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
@@ -798,27 +798,27 @@ static const u16 pinmux_data[] = {
798798
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
799799

800800
PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
801-
PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X),
802-
PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_X),
801+
PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B),
802+
PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B),
803803

804804
PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
805-
PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X),
806-
PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_X),
805+
PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B),
806+
PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B),
807807

808808
/* IP1SR1 */
809809
PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
810-
PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_X),
811-
PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_X),
810+
PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B),
811+
PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B),
812812
PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B),
813813

814814
PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
815-
PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_X),
816-
PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_X),
815+
PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B),
816+
PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B),
817817
PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B),
818818

819819
PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
820-
PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
821-
PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_X),
820+
PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B),
821+
PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B),
822822

823823
PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
824824

@@ -1598,49 +1598,48 @@ static const unsigned int hscif0_ctrl_mux[] = {
15981598
};
15991599

16001600
/* - HSCIF1 ----------------------------------------------------------------- */
1601-
static const unsigned int hscif1_data_pins[] = {
1602-
/* HRX1, HTX1 */
1601+
static const unsigned int hscif1_data_a_pins[] = {
1602+
/* HRX1_A, HTX1_A */
16031603
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
16041604
};
1605-
static const unsigned int hscif1_data_mux[] = {
1606-
HRX1_MARK, HTX1_MARK,
1605+
static const unsigned int hscif1_data_a_mux[] = {
1606+
HRX1_A_MARK, HTX1_A_MARK,
16071607
};
1608-
static const unsigned int hscif1_clk_pins[] = {
1609-
/* HSCK1 */
1608+
static const unsigned int hscif1_clk_a_pins[] = {
1609+
/* HSCK1_A */
16101610
RCAR_GP_PIN(0, 18),
16111611
};
1612-
static const unsigned int hscif1_clk_mux[] = {
1613-
HSCK1_MARK,
1612+
static const unsigned int hscif1_clk_a_mux[] = {
1613+
HSCK1_A_MARK,
16141614
};
1615-
static const unsigned int hscif1_ctrl_pins[] = {
1616-
/* HRTS1_N, HCTS1_N */
1615+
static const unsigned int hscif1_ctrl_a_pins[] = {
1616+
/* HRTS1_N_A, HCTS1_N_A */
16171617
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
16181618
};
1619-
static const unsigned int hscif1_ctrl_mux[] = {
1620-
HRTS1_N_MARK, HCTS1_N_MARK,
1619+
static const unsigned int hscif1_ctrl_a_mux[] = {
1620+
HRTS1_N_A_MARK, HCTS1_N_A_MARK,
16211621
};
16221622

1623-
/* - HSCIF1_X---------------------------------------------------------------- */
1624-
static const unsigned int hscif1_data_x_pins[] = {
1625-
/* HRX1_X, HTX1_X */
1623+
static const unsigned int hscif1_data_b_pins[] = {
1624+
/* HRX1_B, HTX1_B */
16261625
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
16271626
};
1628-
static const unsigned int hscif1_data_x_mux[] = {
1629-
HRX1_X_MARK, HTX1_X_MARK,
1627+
static const unsigned int hscif1_data_b_mux[] = {
1628+
HRX1_B_MARK, HTX1_B_MARK,
16301629
};
1631-
static const unsigned int hscif1_clk_x_pins[] = {
1632-
/* HSCK1_X */
1630+
static const unsigned int hscif1_clk_b_pins[] = {
1631+
/* HSCK1_B */
16331632
RCAR_GP_PIN(1, 10),
16341633
};
1635-
static const unsigned int hscif1_clk_x_mux[] = {
1636-
HSCK1_X_MARK,
1634+
static const unsigned int hscif1_clk_b_mux[] = {
1635+
HSCK1_B_MARK,
16371636
};
1638-
static const unsigned int hscif1_ctrl_x_pins[] = {
1639-
/* HRTS1_N_X, HCTS1_N_X */
1637+
static const unsigned int hscif1_ctrl_b_pins[] = {
1638+
/* HRTS1_N_B, HCTS1_N_B */
16401639
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
16411640
};
1642-
static const unsigned int hscif1_ctrl_x_mux[] = {
1643-
HRTS1_N_X_MARK, HCTS1_N_X_MARK,
1641+
static const unsigned int hscif1_ctrl_b_mux[] = {
1642+
HRTS1_N_B_MARK, HCTS1_N_B_MARK,
16441643
};
16451644

16461645
/* - HSCIF2 ----------------------------------------------------------------- */
@@ -2260,49 +2259,48 @@ static const unsigned int scif0_ctrl_mux[] = {
22602259
};
22612260

22622261
/* - SCIF1 ------------------------------------------------------------------ */
2263-
static const unsigned int scif1_data_pins[] = {
2264-
/* RX1, TX1 */
2262+
static const unsigned int scif1_data_a_pins[] = {
2263+
/* RX1_A, TX1_A */
22652264
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
22662265
};
2267-
static const unsigned int scif1_data_mux[] = {
2268-
RX1_MARK, TX1_MARK,
2266+
static const unsigned int scif1_data_a_mux[] = {
2267+
RX1_A_MARK, TX1_A_MARK,
22692268
};
2270-
static const unsigned int scif1_clk_pins[] = {
2271-
/* SCK1 */
2269+
static const unsigned int scif1_clk_a_pins[] = {
2270+
/* SCK1_A */
22722271
RCAR_GP_PIN(0, 18),
22732272
};
2274-
static const unsigned int scif1_clk_mux[] = {
2275-
SCK1_MARK,
2273+
static const unsigned int scif1_clk_a_mux[] = {
2274+
SCK1_A_MARK,
22762275
};
2277-
static const unsigned int scif1_ctrl_pins[] = {
2278-
/* RTS1_N, CTS1_N */
2276+
static const unsigned int scif1_ctrl_a_pins[] = {
2277+
/* RTS1_N_A, CTS1_N_A */
22792278
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
22802279
};
2281-
static const unsigned int scif1_ctrl_mux[] = {
2282-
RTS1_N_MARK, CTS1_N_MARK,
2280+
static const unsigned int scif1_ctrl_a_mux[] = {
2281+
RTS1_N_A_MARK, CTS1_N_A_MARK,
22832282
};
22842283

2285-
/* - SCIF1_X ------------------------------------------------------------------ */
2286-
static const unsigned int scif1_data_x_pins[] = {
2287-
/* RX1_X, TX1_X */
2284+
static const unsigned int scif1_data_b_pins[] = {
2285+
/* RX1_B, TX1_B */
22882286
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
22892287
};
2290-
static const unsigned int scif1_data_x_mux[] = {
2291-
RX1_X_MARK, TX1_X_MARK,
2288+
static const unsigned int scif1_data_b_mux[] = {
2289+
RX1_B_MARK, TX1_B_MARK,
22922290
};
2293-
static const unsigned int scif1_clk_x_pins[] = {
2294-
/* SCK1_X */
2291+
static const unsigned int scif1_clk_b_pins[] = {
2292+
/* SCK1_B */
22952293
RCAR_GP_PIN(1, 10),
22962294
};
2297-
static const unsigned int scif1_clk_x_mux[] = {
2298-
SCK1_X_MARK,
2295+
static const unsigned int scif1_clk_b_mux[] = {
2296+
SCK1_B_MARK,
22992297
};
2300-
static const unsigned int scif1_ctrl_x_pins[] = {
2301-
/* RTS1_N_X, CTS1_N_X */
2298+
static const unsigned int scif1_ctrl_b_pins[] = {
2299+
/* RTS1_N_B, CTS1_N_B */
23022300
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
23032301
};
2304-
static const unsigned int scif1_ctrl_x_mux[] = {
2305-
RTS1_N_X_MARK, CTS1_N_X_MARK,
2302+
static const unsigned int scif1_ctrl_b_mux[] = {
2303+
RTS1_N_B_MARK, CTS1_N_B_MARK,
23062304
};
23072305

23082306
/* - SCIF3 ------------------------------------------------------------------ */
@@ -2586,12 +2584,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
25862584
SH_PFC_PIN_GROUP(hscif0_data),
25872585
SH_PFC_PIN_GROUP(hscif0_clk),
25882586
SH_PFC_PIN_GROUP(hscif0_ctrl),
2589-
SH_PFC_PIN_GROUP(hscif1_data), /* suffix might be updated */
2590-
SH_PFC_PIN_GROUP(hscif1_clk), /* suffix might be updated */
2591-
SH_PFC_PIN_GROUP(hscif1_ctrl), /* suffix might be updated */
2592-
SH_PFC_PIN_GROUP(hscif1_data_x), /* suffix might be updated */
2593-
SH_PFC_PIN_GROUP(hscif1_clk_x), /* suffix might be updated */
2594-
SH_PFC_PIN_GROUP(hscif1_ctrl_x), /* suffix might be updated */
2587+
SH_PFC_PIN_GROUP(hscif1_data_a),
2588+
SH_PFC_PIN_GROUP(hscif1_clk_a),
2589+
SH_PFC_PIN_GROUP(hscif1_ctrl_a),
2590+
SH_PFC_PIN_GROUP(hscif1_data_b),
2591+
SH_PFC_PIN_GROUP(hscif1_clk_b),
2592+
SH_PFC_PIN_GROUP(hscif1_ctrl_b),
25952593
SH_PFC_PIN_GROUP(hscif2_data),
25962594
SH_PFC_PIN_GROUP(hscif2_clk),
25972595
SH_PFC_PIN_GROUP(hscif2_ctrl),
@@ -2685,12 +2683,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
26852683
SH_PFC_PIN_GROUP(scif0_data),
26862684
SH_PFC_PIN_GROUP(scif0_clk),
26872685
SH_PFC_PIN_GROUP(scif0_ctrl),
2688-
SH_PFC_PIN_GROUP(scif1_data), /* suffix might be updated */
2689-
SH_PFC_PIN_GROUP(scif1_clk), /* suffix might be updated */
2690-
SH_PFC_PIN_GROUP(scif1_ctrl), /* suffix might be updated */
2691-
SH_PFC_PIN_GROUP(scif1_data_x), /* suffix might be updated */
2692-
SH_PFC_PIN_GROUP(scif1_clk_x), /* suffix might be updated */
2693-
SH_PFC_PIN_GROUP(scif1_ctrl_x), /* suffix might be updated */
2686+
SH_PFC_PIN_GROUP(scif1_data_a),
2687+
SH_PFC_PIN_GROUP(scif1_clk_a),
2688+
SH_PFC_PIN_GROUP(scif1_ctrl_a),
2689+
SH_PFC_PIN_GROUP(scif1_data_b),
2690+
SH_PFC_PIN_GROUP(scif1_clk_b),
2691+
SH_PFC_PIN_GROUP(scif1_ctrl_b),
26942692
SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */
26952693
SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */
26962694
SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */
@@ -2810,13 +2808,12 @@ static const char * const hscif0_groups[] = {
28102808
};
28112809

28122810
static const char * const hscif1_groups[] = {
2813-
/* suffix might be updated */
2814-
"hscif1_data",
2815-
"hscif1_clk",
2816-
"hscif1_ctrl",
2817-
"hscif1_data_x",
2818-
"hscif1_clk_x",
2819-
"hscif1_ctrl_x",
2811+
"hscif1_data_a",
2812+
"hscif1_clk_a",
2813+
"hscif1_ctrl_a",
2814+
"hscif1_data_b",
2815+
"hscif1_clk_b",
2816+
"hscif1_ctrl_b",
28202817
};
28212818

28222819
static const char * const hscif2_groups[] = {
@@ -2993,13 +2990,12 @@ static const char * const scif0_groups[] = {
29932990
};
29942991

29952992
static const char * const scif1_groups[] = {
2996-
/* suffix might be updated */
2997-
"scif1_data",
2998-
"scif1_clk",
2999-
"scif1_ctrl",
3000-
"scif1_data_x",
3001-
"scif1_clk_x",
3002-
"scif1_ctrl_x",
2993+
"scif1_data_a",
2994+
"scif1_clk_a",
2995+
"scif1_ctrl_a",
2996+
"scif1_data_b",
2997+
"scif1_clk_b",
2998+
"scif1_ctrl_b",
30032999
};
30043000

30053001
static const char * const scif3_groups[] = {

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