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Wenjing Liualexdeucher
Wenjing Liu
authored and
alexdeucher
committed
drm/amd/display: access hpo dp link encoder only through link resource
[why] Update all accesses to use hpo dp link encoder through link resource only. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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7 files changed

+40
-43
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7 files changed

+40
-43
lines changed

‎drivers/gpu/drm/amd/display/dc/core/dc_link.c

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3426,7 +3426,7 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
34263426
{
34273427
struct dc_stream_state *stream = pipe_ctx->stream;
34283428
struct dc_link *link = stream->link;
3429-
struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3429+
struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
34303430
struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
34313431
struct link_mst_stream_allocation_table proposed_table = {0};
34323432
struct fixed31_32 avg_time_slots_per_mtp;
@@ -3508,7 +3508,7 @@ enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
35083508
struct link_encoder *link_encoder = NULL;
35093509
struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
35103510
#if defined(CONFIG_DRM_AMD_DC_DCN)
3511-
struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3511+
struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
35123512
struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
35133513
#endif
35143514
struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -3838,7 +3838,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
38383838
struct link_encoder *link_encoder = NULL;
38393839
struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
38403840
#if defined(CONFIG_DRM_AMD_DC_DCN)
3841-
struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3841+
struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
38423842
struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
38433843
#endif
38443844
struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -4164,12 +4164,12 @@ static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pi
41644164
proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
41654165
}
41664166

4167-
stream->link->hpo_dp_link_enc->funcs->update_stream_allocation_table(
4168-
stream->link->hpo_dp_link_enc,
4167+
pipe_ctx->link_res.hpo_dp_link_enc->funcs->update_stream_allocation_table(
4168+
pipe_ctx->link_res.hpo_dp_link_enc,
41694169
&proposed_table);
41704170

4171-
stream->link->hpo_dp_link_enc->funcs->set_throttled_vcp_size(
4172-
stream->link->hpo_dp_link_enc,
4171+
pipe_ctx->link_res.hpo_dp_link_enc->funcs->set_throttled_vcp_size(
4172+
pipe_ctx->link_res.hpo_dp_link_enc,
41734173
pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
41744174
avg_time_slots_per_mtp);
41754175

@@ -4674,11 +4674,9 @@ void dc_link_set_preferred_training_settings(struct dc *dc,
46744674
if (link_setting != NULL) {
46754675
link->preferred_link_setting = *link_setting;
46764676
#if defined(CONFIG_DRM_AMD_DC_DCN)
4677-
if (dp_get_link_encoding_format(link_setting) ==
4678-
DP_128b_132b_ENCODING && !link->hpo_dp_link_enc) {
4679-
if (!add_dp_hpo_link_encoder_to_link(link))
4680-
memset(&link->preferred_link_setting, 0, sizeof(link->preferred_link_setting));
4681-
}
4677+
if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4678+
/* TODO: add dc update for acquiring link res */
4679+
skip_immediate_retrain = true;
46824680
#endif
46834681
} else {
46844682
link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;

‎drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3211,9 +3211,11 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link,
32113211
if (link_enc)
32123212
link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
32133213
#if defined(CONFIG_DRM_AMD_DC_DCN)
3214-
if (max_link_cap.link_rate >= LINK_RATE_UHBR10 &&
3215-
!link->hpo_dp_link_enc)
3216-
max_link_cap.link_rate = LINK_RATE_HIGH3;
3214+
if (max_link_cap.link_rate >= LINK_RATE_UHBR10) {
3215+
if (!link_res->hpo_dp_link_enc ||
3216+
link->dc->debug.disable_uhbr)
3217+
max_link_cap.link_rate = LINK_RATE_HIGH3;
3218+
}
32173219
#endif
32183220

32193221
/* Lower link settings based on sink's link cap */
@@ -7016,8 +7018,10 @@ struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
70167018

70177019
bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
70187020
{
7021+
/* If this assert is hit then we have a link encoder dynamic management issue */
7022+
ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
70197023
return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
7020-
pipe_ctx->stream->link->hpo_dp_link_enc &&
7024+
pipe_ctx->link_res.hpo_dp_link_enc &&
70217025
dc_is_dp_signal(pipe_ctx->stream->signal));
70227026
}
70237027
#endif

‎drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -243,7 +243,7 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_
243243
struct dc *dc = link->ctx->dc;
244244
struct dmcu *dmcu = dc->res_pool->dmcu;
245245
#if defined(CONFIG_DRM_AMD_DC_DCN)
246-
struct hpo_dp_link_encoder *hpo_link_enc = link->hpo_dp_link_enc;
246+
struct hpo_dp_link_encoder *hpo_link_enc = link_res->hpo_dp_link_enc;
247247
#endif
248248
struct link_encoder *link_enc;
249249

@@ -366,8 +366,8 @@ void dp_set_hw_lane_settings(
366366
#if defined(CONFIG_DRM_AMD_DC_DCN)
367367
if (dp_get_link_encoding_format(&link_settings->link_settings) ==
368368
DP_128b_132b_ENCODING) {
369-
link->hpo_dp_link_enc->funcs->set_ffe(
370-
link->hpo_dp_link_enc,
369+
link_res->hpo_dp_link_enc->funcs->set_ffe(
370+
link_res->hpo_dp_link_enc,
371371
&link_settings->link_settings,
372372
link_settings->lane_settings[0].FFE_PRESET.raw);
373373
} else if (dp_get_link_encoding_format(&link_settings->link_settings)
@@ -412,8 +412,8 @@ void dp_set_hw_test_pattern(
412412
#if defined(CONFIG_DRM_AMD_DC_DCN)
413413
switch (link_encoding_format) {
414414
case DP_128b_132b_ENCODING:
415-
link->hpo_dp_link_enc->funcs->set_link_test_pattern(
416-
link->hpo_dp_link_enc, &pattern_param);
415+
link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
416+
link_res->hpo_dp_link_enc, &pattern_param);
417417
break;
418418
case DP_8b_10b_ENCODING:
419419
ASSERT(encoder);
@@ -797,8 +797,8 @@ void enable_dp_hpo_output(struct dc_link *link,
797797
}
798798
} else {
799799
/* DP2.0 HW: call transmitter control to enable PHY */
800-
link->hpo_dp_link_enc->funcs->enable_link_phy(
801-
link->hpo_dp_link_enc,
800+
link_res->hpo_dp_link_enc->funcs->enable_link_phy(
801+
link_res->hpo_dp_link_enc,
802802
link_settings,
803803
link->link_enc->transmitter);
804804
}
@@ -814,11 +814,11 @@ void enable_dp_hpo_output(struct dc_link *link,
814814
phyd32clk = get_phyd32clk_src(link);
815815
dc->res_pool->dccg->funcs->enable_symclk32_le(
816816
dc->res_pool->dccg,
817-
link->hpo_dp_link_enc->inst,
817+
link_res->hpo_dp_link_enc->inst,
818818
phyd32clk);
819-
link->hpo_dp_link_enc->funcs->link_enable(
820-
link->hpo_dp_link_enc,
821-
link_settings->lane_count);
819+
link_res->hpo_dp_link_enc->funcs->link_enable(
820+
link_res->hpo_dp_link_enc,
821+
link_settings->lane_count);
822822
}
823823
}
824824

@@ -828,12 +828,12 @@ void disable_dp_hpo_output(struct dc_link *link,
828828
{
829829
const struct dc *dc = link->dc;
830830

831-
link->hpo_dp_link_enc->funcs->link_disable(link->hpo_dp_link_enc);
831+
link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc);
832832

833833
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
834834
dc->res_pool->dccg->funcs->disable_symclk32_le(
835835
dc->res_pool->dccg,
836-
link->hpo_dp_link_enc->inst);
836+
link_res->hpo_dp_link_enc->inst);
837837

838838
dc->res_pool->dccg->funcs->set_physymclk(
839839
dc->res_pool->dccg,
@@ -844,8 +844,8 @@ void disable_dp_hpo_output(struct dc_link *link,
844844
dm_set_phyd32clk(dc->ctx, 0);
845845
} else {
846846
/* DP2.0 HW: call transmitter control to disable PHY */
847-
link->hpo_dp_link_enc->funcs->disable_link_phy(
848-
link->hpo_dp_link_enc,
847+
link_res->hpo_dp_link_enc->funcs->disable_link_phy(
848+
link_res->hpo_dp_link_enc,
849849
signal);
850850
}
851851
}

‎drivers/gpu/drm/amd/display/dc/dc.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -691,6 +691,7 @@ struct dc_debug_options {
691691
/* TODO - remove once tested */
692692
bool legacy_dp2_lt;
693693
bool set_mst_en_for_sst;
694+
bool disable_uhbr;
694695
bool force_dp2_lt_fallback_method;
695696
#endif
696697
union mem_low_power_enable_options enable_mem_low_power;

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -468,8 +468,6 @@ void dcn10_log_hw_state(struct dc *dc,
468468
log_mpc_crc(dc, log_ctx);
469469

470470
{
471-
int hpo_dp_link_enc_count = 0;
472-
473471
if (pool->hpo_dp_stream_enc_count > 0) {
474472
DTN_INFO("DP HPO S_ENC: Enabled OTG Format Depth Vid SDP Compressed Link\n");
475473
for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
@@ -500,18 +498,14 @@ void dcn10_log_hw_state(struct dc *dc,
500498
}
501499

502500
/* log DP HPO L_ENC section if any hpo_dp_link_enc exists */
503-
for (i = 0; i < dc->link_count; i++)
504-
if (dc->links[i]->hpo_dp_link_enc)
505-
hpo_dp_link_enc_count++;
506-
507-
if (hpo_dp_link_enc_count) {
501+
if (pool->hpo_dp_link_enc_count) {
508502
DTN_INFO("DP HPO L_ENC: Enabled Mode Lanes Stream Slots VC Rate X VC Rate Y\n");
509503

510-
for (i = 0; i < dc->link_count; i++) {
511-
struct hpo_dp_link_encoder *hpo_dp_link_enc = dc->links[i]->hpo_dp_link_enc;
504+
for (i = 0; i < pool->hpo_dp_link_enc_count; i++) {
505+
struct hpo_dp_link_encoder *hpo_dp_link_enc = pool->hpo_dp_link_enc[i];
512506
struct hpo_dp_link_enc_state hpo_dp_le_state = {0};
513507

514-
if (hpo_dp_link_enc && hpo_dp_link_enc->funcs->read_state) {
508+
if (hpo_dp_link_enc->funcs->read_state) {
515509
hpo_dp_link_enc->funcs->read_state(hpo_dp_link_enc, &hpo_dp_le_state);
516510
DTN_INFO("[%d]: %d %6s %d %d %d %d %d\n",
517511
hpo_dp_link_enc->inst,

‎drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2414,7 +2414,7 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
24142414
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->map_stream_to_link(
24152415
pipe_ctx->stream_res.hpo_dp_stream_enc,
24162416
pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
2417-
link->hpo_dp_link_enc->inst);
2417+
pipe_ctx->link_res.hpo_dp_link_enc->inst);
24182418
}
24192419

24202420
if (!is_dp_128b_132b_signal(pipe_ctx) && link_enc)

‎drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1274,7 +1274,7 @@ static void dcn20_adjust_adaptive_sync_v_startup(
12741274
static bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
12751275
{
12761276
return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
1277-
pipe_ctx->stream->link->hpo_dp_link_enc &&
1277+
pipe_ctx->link_res.hpo_dp_link_enc &&
12781278
dc_is_dp_signal(pipe_ctx->stream->signal));
12791279
}
12801280

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