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fredlawlbjorn-helgaas
fredlawl
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bjorn-helgaas
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drm/radeon: Prefer pcie_capability_read_word()
Commit 8c0d3a0 ("PCI: Add accessors for PCI Express Capability") added accessors for the PCI Express Capability so that drivers didn't need to be aware of differences between v1 and v2 of the PCI Express Capability. Replace pci_read_config_word() and pci_write_config_word() calls with pcie_capability_read_word() and pcie_capability_write_word(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frederick Lawler <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
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-53
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2 files changed

+90
-53
lines changed

‎drivers/gpu/drm/radeon/cik.c

Lines changed: 44 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -9504,7 +9504,6 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
95049504
{
95059505
struct pci_dev *root = rdev->pdev->bus->self;
95069506
enum pci_bus_speed speed_cap;
9507-
int bridge_pos, gpu_pos;
95089507
u32 speed_cntl, current_data_rate;
95099508
int i;
95109509
u16 tmp16;
@@ -9546,12 +9545,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
95469545
DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
95479546
}
95489547

9549-
bridge_pos = pci_pcie_cap(root);
9550-
if (!bridge_pos)
9551-
return;
9552-
9553-
gpu_pos = pci_pcie_cap(rdev->pdev);
9554-
if (!gpu_pos)
9548+
if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
95559549
return;
95569550

95579551
if (speed_cap == PCIE_SPEED_8_0GT) {
@@ -9561,14 +9555,17 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
95619555
u16 bridge_cfg2, gpu_cfg2;
95629556
u32 max_lw, current_lw, tmp;
95639557

9564-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
9565-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
9558+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9559+
&bridge_cfg);
9560+
pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
9561+
&gpu_cfg);
95669562

95679563
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
9568-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
9564+
pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
95699565

95709566
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
9571-
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
9567+
pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
9568+
tmp16);
95729569

95739570
tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
95749571
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -9586,15 +9583,23 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
95869583

95879584
for (i = 0; i < 10; i++) {
95889585
/* check status */
9589-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
9586+
pcie_capability_read_word(rdev->pdev,
9587+
PCI_EXP_DEVSTA,
9588+
&tmp16);
95909589
if (tmp16 & PCI_EXP_DEVSTA_TRPND)
95919590
break;
95929591

9593-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
9594-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
9592+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9593+
&bridge_cfg);
9594+
pcie_capability_read_word(rdev->pdev,
9595+
PCI_EXP_LNKCTL,
9596+
&gpu_cfg);
95959597

9596-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
9597-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
9598+
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
9599+
&bridge_cfg2);
9600+
pcie_capability_read_word(rdev->pdev,
9601+
PCI_EXP_LNKCTL2,
9602+
&gpu_cfg2);
95989603

95999604
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
96009605
tmp |= LC_SET_QUIESCE;
@@ -9607,32 +9612,45 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
96079612
msleep(100);
96089613

96099614
/* linkctl */
9610-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
9615+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9616+
&tmp16);
96119617
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
96129618
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
9613-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
9619+
pcie_capability_write_word(root, PCI_EXP_LNKCTL,
9620+
tmp16);
96149621

9615-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
9622+
pcie_capability_read_word(rdev->pdev,
9623+
PCI_EXP_LNKCTL,
9624+
&tmp16);
96169625
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
96179626
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
9618-
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
9627+
pcie_capability_write_word(rdev->pdev,
9628+
PCI_EXP_LNKCTL,
9629+
tmp16);
96199630

96209631
/* linkctl2 */
9621-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
9632+
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
9633+
&tmp16);
96229634
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
96239635
PCI_EXP_LNKCTL2_TX_MARGIN);
96249636
tmp16 |= (bridge_cfg2 &
96259637
(PCI_EXP_LNKCTL2_ENTER_COMP |
96269638
PCI_EXP_LNKCTL2_TX_MARGIN));
9627-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
9639+
pcie_capability_write_word(root,
9640+
PCI_EXP_LNKCTL2,
9641+
tmp16);
96289642

9629-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9643+
pcie_capability_read_word(rdev->pdev,
9644+
PCI_EXP_LNKCTL2,
9645+
&tmp16);
96309646
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
96319647
PCI_EXP_LNKCTL2_TX_MARGIN);
96329648
tmp16 |= (gpu_cfg2 &
96339649
(PCI_EXP_LNKCTL2_ENTER_COMP |
96349650
PCI_EXP_LNKCTL2_TX_MARGIN));
9635-
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9651+
pcie_capability_write_word(rdev->pdev,
9652+
PCI_EXP_LNKCTL2,
9653+
tmp16);
96369654

96379655
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
96389656
tmp &= ~LC_SET_QUIESCE;
@@ -9646,15 +9664,15 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
96469664
speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
96479665
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
96489666

9649-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9667+
pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
96509668
tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
96519669
if (speed_cap == PCIE_SPEED_8_0GT)
96529670
tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
96539671
else if (speed_cap == PCIE_SPEED_5_0GT)
96549672
tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
96559673
else
96569674
tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
9657-
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9675+
pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
96589676

96599677
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
96609678
speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

‎drivers/gpu/drm/radeon/si.c

Lines changed: 46 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -3257,7 +3257,7 @@ static void si_gpu_init(struct radeon_device *rdev)
32573257
/* XXX what about 12? */
32583258
rdev->config.si.tile_config |= (3 << 0);
32593259
break;
3260-
}
3260+
}
32613261
switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
32623262
case 0: /* four banks */
32633263
rdev->config.si.tile_config |= 0 << 4;
@@ -7087,7 +7087,6 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
70877087
{
70887088
struct pci_dev *root = rdev->pdev->bus->self;
70897089
enum pci_bus_speed speed_cap;
7090-
int bridge_pos, gpu_pos;
70917090
u32 speed_cntl, current_data_rate;
70927091
int i;
70937092
u16 tmp16;
@@ -7129,12 +7128,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
71297128
DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
71307129
}
71317130

7132-
bridge_pos = pci_pcie_cap(root);
7133-
if (!bridge_pos)
7134-
return;
7135-
7136-
gpu_pos = pci_pcie_cap(rdev->pdev);
7137-
if (!gpu_pos)
7131+
if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
71387132
return;
71397133

71407134
if (speed_cap == PCIE_SPEED_8_0GT) {
@@ -7144,14 +7138,17 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
71447138
u16 bridge_cfg2, gpu_cfg2;
71457139
u32 max_lw, current_lw, tmp;
71467140

7147-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7148-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7141+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
7142+
&bridge_cfg);
7143+
pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
7144+
&gpu_cfg);
71497145

71507146
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
7151-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7147+
pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
71527148

71537149
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
7154-
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7150+
pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
7151+
tmp16);
71557152

71567153
tmp = RREG32_PCIE(PCIE_LC_STATUS1);
71577154
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -7169,15 +7166,23 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
71697166

71707167
for (i = 0; i < 10; i++) {
71717168
/* check status */
7172-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
7169+
pcie_capability_read_word(rdev->pdev,
7170+
PCI_EXP_DEVSTA,
7171+
&tmp16);
71737172
if (tmp16 & PCI_EXP_DEVSTA_TRPND)
71747173
break;
71757174

7176-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7177-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7175+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
7176+
&bridge_cfg);
7177+
pcie_capability_read_word(rdev->pdev,
7178+
PCI_EXP_LNKCTL,
7179+
&gpu_cfg);
71787180

7179-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
7180-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
7181+
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
7182+
&bridge_cfg2);
7183+
pcie_capability_read_word(rdev->pdev,
7184+
PCI_EXP_LNKCTL2,
7185+
&gpu_cfg2);
71817186

71827187
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
71837188
tmp |= LC_SET_QUIESCE;
@@ -7190,32 +7195,46 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
71907195
msleep(100);
71917196

71927197
/* linkctl */
7193-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
7198+
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
7199+
&tmp16);
71947200
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
71957201
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
7196-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7202+
pcie_capability_write_word(root,
7203+
PCI_EXP_LNKCTL,
7204+
tmp16);
71977205

7198-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
7206+
pcie_capability_read_word(rdev->pdev,
7207+
PCI_EXP_LNKCTL,
7208+
&tmp16);
71997209
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
72007210
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
7201-
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7211+
pcie_capability_write_word(rdev->pdev,
7212+
PCI_EXP_LNKCTL,
7213+
tmp16);
72027214

72037215
/* linkctl2 */
7204-
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
7216+
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
7217+
&tmp16);
72057218
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
72067219
PCI_EXP_LNKCTL2_TX_MARGIN);
72077220
tmp16 |= (bridge_cfg2 &
72087221
(PCI_EXP_LNKCTL2_ENTER_COMP |
72097222
PCI_EXP_LNKCTL2_TX_MARGIN));
7210-
pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
7223+
pcie_capability_write_word(root,
7224+
PCI_EXP_LNKCTL2,
7225+
tmp16);
72117226

7212-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7227+
pcie_capability_read_word(rdev->pdev,
7228+
PCI_EXP_LNKCTL2,
7229+
&tmp16);
72137230
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
72147231
PCI_EXP_LNKCTL2_TX_MARGIN);
72157232
tmp16 |= (gpu_cfg2 &
72167233
(PCI_EXP_LNKCTL2_ENTER_COMP |
72177234
PCI_EXP_LNKCTL2_TX_MARGIN));
7218-
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7235+
pcie_capability_write_word(rdev->pdev,
7236+
PCI_EXP_LNKCTL2,
7237+
tmp16);
72197238

72207239
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
72217240
tmp &= ~LC_SET_QUIESCE;
@@ -7229,15 +7248,15 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
72297248
speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
72307249
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
72317250

7232-
pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7251+
pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
72337252
tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
72347253
if (speed_cap == PCIE_SPEED_8_0GT)
72357254
tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
72367255
else if (speed_cap == PCIE_SPEED_5_0GT)
72377256
tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
72387257
else
72397258
tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
7240-
pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7259+
pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
72417260

72427261
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
72437262
speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

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