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Merge tag 'mlx5-fixes-2024-09-09' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux
Saeed Mahameed says: ==================== mlx5 fixes 2024-09-09 This series provides bug fixes to mlx5 driver. * tag 'mlx5-fixes-2024-09-09' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux: net/mlx5: Fix bridge mode operations when there are no VFs net/mlx5: Verify support for scheduling element and TSAR type net/mlx5: Add missing masks and QoS bit masks for scheduling elements net/mlx5: Explicitly set scheduling element and TSAR type net/mlx5e: Add missing link mode to ptys2ext_ethtool_map net/mlx5e: Add missing link modes to ptys2ethtool_map net/mlx5: Update the list of the PCI supported devices ==================== Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2 parents 330dada + b1d305a commit 3d731dc

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-23
lines changed

6 files changed

+60
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‎drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,10 @@ void mlx5e_build_ptys2ethtool_map(void)
139139
ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
140140
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
141141
ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
142+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy,
143+
ETHTOOL_LINK_MODE_100baseT_Full_BIT);
144+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy,
145+
ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
142146
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
143147
ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
144148
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
@@ -204,6 +208,12 @@ void mlx5e_build_ptys2ethtool_map(void)
204208
ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
205209
ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
206210
ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
211+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext,
212+
ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
213+
ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
214+
ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
215+
ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
216+
ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT);
207217
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
208218
ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
209219
ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,

‎drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting)
319319
return -EPERM;
320320

321321
mutex_lock(&esw->state_lock);
322-
if (esw->mode != MLX5_ESWITCH_LEGACY) {
322+
if (esw->mode != MLX5_ESWITCH_LEGACY || !mlx5_esw_is_fdb_created(esw)) {
323323
err = -EOPNOTSUPP;
324324
goto out;
325325
}
@@ -339,7 +339,7 @@ int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting)
339339
if (!mlx5_esw_allowed(esw))
340340
return -EPERM;
341341

342-
if (esw->mode != MLX5_ESWITCH_LEGACY)
342+
if (esw->mode != MLX5_ESWITCH_LEGACY || !mlx5_esw_is_fdb_created(esw))
343343
return -EOPNOTSUPP;
344344

345345
*setting = esw->fdb_table.legacy.vepa_uplink_rule ? 1 : 0;

‎drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c

Lines changed: 31 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -312,6 +312,25 @@ static int esw_qos_set_group_max_rate(struct mlx5_eswitch *esw,
312312
return err;
313313
}
314314

315+
static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)
316+
{
317+
switch (type) {
318+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
319+
return MLX5_CAP_QOS(dev, esw_element_type) &
320+
ELEMENT_TYPE_CAP_MASK_TSAR;
321+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
322+
return MLX5_CAP_QOS(dev, esw_element_type) &
323+
ELEMENT_TYPE_CAP_MASK_VPORT;
324+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
325+
return MLX5_CAP_QOS(dev, esw_element_type) &
326+
ELEMENT_TYPE_CAP_MASK_VPORT_TC;
327+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
328+
return MLX5_CAP_QOS(dev, esw_element_type) &
329+
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
330+
}
331+
return false;
332+
}
333+
315334
static int esw_qos_vport_create_sched_element(struct mlx5_eswitch *esw,
316335
struct mlx5_vport *vport,
317336
u32 max_rate, u32 bw_share)
@@ -323,6 +342,9 @@ static int esw_qos_vport_create_sched_element(struct mlx5_eswitch *esw,
323342
void *vport_elem;
324343
int err;
325344

345+
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT))
346+
return -EOPNOTSUPP;
347+
326348
parent_tsar_ix = group ? group->tsar_ix : esw->qos.root_tsar_ix;
327349
MLX5_SET(scheduling_context, sched_ctx, element_type,
328350
SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT);
@@ -421,13 +443,20 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex
421443
{
422444
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
423445
struct mlx5_esw_rate_group *group;
446+
__be32 *attr;
424447
u32 divider;
425448
int err;
426449

427450
group = kzalloc(sizeof(*group), GFP_KERNEL);
428451
if (!group)
429452
return ERR_PTR(-ENOMEM);
430453

454+
MLX5_SET(scheduling_context, tsar_ctx, element_type,
455+
SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);
456+
457+
attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);
458+
*attr = cpu_to_be32(TSAR_ELEMENT_TSAR_TYPE_DWRR << 16);
459+
431460
MLX5_SET(scheduling_context, tsar_ctx, parent_element_id,
432461
esw->qos.root_tsar_ix);
433462
err = mlx5_create_scheduling_element_cmd(esw->dev,
@@ -526,25 +555,6 @@ static int esw_qos_destroy_rate_group(struct mlx5_eswitch *esw,
526555
return err;
527556
}
528557

529-
static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)
530-
{
531-
switch (type) {
532-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
533-
return MLX5_CAP_QOS(dev, esw_element_type) &
534-
ELEMENT_TYPE_CAP_MASK_TSAR;
535-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
536-
return MLX5_CAP_QOS(dev, esw_element_type) &
537-
ELEMENT_TYPE_CAP_MASK_VPORT;
538-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
539-
return MLX5_CAP_QOS(dev, esw_element_type) &
540-
ELEMENT_TYPE_CAP_MASK_VPORT_TC;
541-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
542-
return MLX5_CAP_QOS(dev, esw_element_type) &
543-
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
544-
}
545-
return false;
546-
}
547-
548558
static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack)
549559
{
550560
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
@@ -555,7 +565,8 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta
555565
if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
556566
return -EOPNOTSUPP;
557567

558-
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR))
568+
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR) ||
569+
!(MLX5_CAP_QOS(dev, esw_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
559570
return -EOPNOTSUPP;
560571

561572
MLX5_SET(scheduling_context, tsar_ctx, element_type,

‎drivers/net/ethernet/mellanox/mlx5/core/main.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2217,6 +2217,7 @@ static const struct pci_device_id mlx5_core_pci_table[] = {
22172217
{ PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
22182218
{ PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
22192219
{ PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2220+
{ PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
22202221
{ PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
22212222
{ PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
22222223
{ PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */

‎drivers/net/ethernet/mellanox/mlx5/core/qos.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,9 @@ int mlx5_qos_create_leaf_node(struct mlx5_core_dev *mdev, u32 parent_id,
2828
{
2929
u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
3030

31+
if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP))
32+
return -EOPNOTSUPP;
33+
3134
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
3235
MLX5_SET(scheduling_context, sched_ctx, element_type,
3336
SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP);
@@ -44,6 +47,10 @@ int mlx5_qos_create_inner_node(struct mlx5_core_dev *mdev, u32 parent_id,
4447
u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
4548
void *attr;
4649

50+
if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_TSAR) ||
51+
!(MLX5_CAP_QOS(mdev, nic_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
52+
return -EOPNOTSUPP;
53+
4754
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
4855
MLX5_SET(scheduling_context, sched_ctx, element_type,
4956
SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);

‎include/linux/mlx5/mlx5_ifc.h

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1027,7 +1027,8 @@ struct mlx5_ifc_qos_cap_bits {
10271027

10281028
u8 max_tsar_bw_share[0x20];
10291029

1030-
u8 reserved_at_100[0x20];
1030+
u8 nic_element_type[0x10];
1031+
u8 nic_tsar_type[0x10];
10311032

10321033
u8 reserved_at_120[0x3];
10331034
u8 log_meter_aso_granularity[0x5];
@@ -3966,6 +3967,7 @@ enum {
39663967
ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
39673968
ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
39683969
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3970+
ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4,
39693971
};
39703972

39713973
struct mlx5_ifc_scheduling_context_bits {
@@ -4675,6 +4677,12 @@ enum {
46754677
TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
46764678
};
46774679

4680+
enum {
4681+
TSAR_TYPE_CAP_MASK_DWRR = 1 << 0,
4682+
TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1,
4683+
TSAR_TYPE_CAP_MASK_ETS = 1 << 2,
4684+
};
4685+
46784686
struct mlx5_ifc_tsar_element_bits {
46794687
u8 reserved_at_0[0x8];
46804688
u8 tsar_type[0x8];

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