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Hao LanPaolo Abeni
Hao Lan
authored and
Paolo Abeni
committed
net: hns3: fixed reset failure issues caused by the incorrect reset type
When a reset type that is not supported by the driver is input, a reset pending flag bit of the HNAE3_NONE_RESET type is generated in reset_pending. The driver does not have a mechanism to clear this type of error. As a result, the driver considers that the reset is not complete. This patch provides a mechanism to clear the HNAE3_NONE_RESET flag and the parameter of hnae3_ae_ops.set_default_reset_request is verified. The error message: hns3 0000:39:01.0: cmd failed -16 hns3 0000:39:01.0: hclge device re-init failed, VF is disabled! hns3 0000:39:01.0: failed to reset VF stack hns3 0000:39:01.0: failed to reset VF(4) hns3 0000:39:01.0: prepare reset(2) wait done hns3 0000:39:01.0 eth4: already uninitialized Use the crash tool to view struct hclgevf_dev: struct hclgevf_dev { ... default_reset_request = 0x20, reset_level = HNAE3_NONE_RESET, reset_pending = 0x100, reset_type = HNAE3_NONE_RESET, ... }; Fixes: 720bd58 ("net: hns3: add set_default_reset_request in the hnae3_ae_ops") Signed-off-by: Hao Lan <[email protected]> Signed-off-by: Jijie Shao <[email protected]> Signed-off-by: Paolo Abeni <[email protected]>
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+61
-10
lines changed

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c‎

Lines changed: 29 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3584,6 +3584,17 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
35843584
return ret;
35853585
}
35863586

3587+
static void hclge_set_reset_pending(struct hclge_dev *hdev,
3588+
enum hnae3_reset_type reset_type)
3589+
{
3590+
/* When an incorrect reset type is executed, the get_reset_level
3591+
* function generates the HNAE3_NONE_RESET flag. As a result, this
3592+
* type do not need to pending.
3593+
*/
3594+
if (reset_type != HNAE3_NONE_RESET)
3595+
set_bit(reset_type, &hdev->reset_pending);
3596+
}
3597+
35873598
static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
35883599
{
35893600
u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
@@ -3604,7 +3615,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
36043615
*/
36053616
if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
36063617
dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
3607-
set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
3618+
hclge_set_reset_pending(hdev, HNAE3_IMP_RESET);
36083619
set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
36093620
*clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
36103621
hdev->rst_stats.imp_rst_cnt++;
@@ -3614,7 +3625,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
36143625
if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
36153626
dev_info(&hdev->pdev->dev, "global reset interrupt\n");
36163627
set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3617-
set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
3628+
hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET);
36183629
*clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
36193630
hdev->rst_stats.global_rst_cnt++;
36203631
return HCLGE_VECTOR0_EVENT_RST;
@@ -4062,7 +4073,7 @@ static void hclge_do_reset(struct hclge_dev *hdev)
40624073
case HNAE3_FUNC_RESET:
40634074
dev_info(&pdev->dev, "PF reset requested\n");
40644075
/* schedule again to check later */
4065-
set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
4076+
hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET);
40664077
hclge_reset_task_schedule(hdev);
40674078
break;
40684079
default:
@@ -4096,6 +4107,8 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
40964107
clear_bit(HNAE3_FLR_RESET, addr);
40974108
}
40984109

4110+
clear_bit(HNAE3_NONE_RESET, addr);
4111+
40994112
if (hdev->reset_type != HNAE3_NONE_RESET &&
41004113
rst_level < hdev->reset_type)
41014114
return HNAE3_NONE_RESET;
@@ -4237,7 +4250,7 @@ static bool hclge_reset_err_handle(struct hclge_dev *hdev)
42374250
return false;
42384251
} else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) {
42394252
hdev->rst_stats.reset_fail_cnt++;
4240-
set_bit(hdev->reset_type, &hdev->reset_pending);
4253+
hclge_set_reset_pending(hdev, hdev->reset_type);
42414254
dev_info(&hdev->pdev->dev,
42424255
"re-schedule reset task(%u)\n",
42434256
hdev->rst_stats.reset_fail_cnt);
@@ -4480,8 +4493,20 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
44804493
static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
44814494
enum hnae3_reset_type rst_type)
44824495
{
4496+
#define HCLGE_SUPPORT_RESET_TYPE \
4497+
(BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \
4498+
BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET))
4499+
44834500
struct hclge_dev *hdev = ae_dev->priv;
44844501

4502+
if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) {
4503+
/* To prevent reset triggered by hclge_reset_event */
4504+
set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request);
4505+
dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n",
4506+
rst_type);
4507+
return;
4508+
}
4509+
44854510
set_bit(rst_type, &hdev->default_reset_request);
44864511
}
44874512

‎drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c‎

Lines changed: 32 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1395,6 +1395,17 @@ static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
13951395
return ret;
13961396
}
13971397

1398+
static void hclgevf_set_reset_pending(struct hclgevf_dev *hdev,
1399+
enum hnae3_reset_type reset_type)
1400+
{
1401+
/* When an incorrect reset type is executed, the get_reset_level
1402+
* function generates the HNAE3_NONE_RESET flag. As a result, this
1403+
* type do not need to pending.
1404+
*/
1405+
if (reset_type != HNAE3_NONE_RESET)
1406+
set_bit(reset_type, &hdev->reset_pending);
1407+
}
1408+
13981409
static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
13991410
{
14001411
#define HCLGEVF_RESET_WAIT_US 20000
@@ -1544,7 +1555,7 @@ static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
15441555
hdev->rst_stats.rst_fail_cnt);
15451556

15461557
if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1547-
set_bit(hdev->reset_type, &hdev->reset_pending);
1558+
hclgevf_set_reset_pending(hdev, hdev->reset_type);
15481559

15491560
if (hclgevf_is_reset_pending(hdev)) {
15501561
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
@@ -1664,6 +1675,8 @@ static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr)
16641675
clear_bit(HNAE3_FLR_RESET, addr);
16651676
}
16661677

1678+
clear_bit(HNAE3_NONE_RESET, addr);
1679+
16671680
return rst_level;
16681681
}
16691682

@@ -1673,14 +1686,15 @@ static void hclgevf_reset_event(struct pci_dev *pdev,
16731686
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
16741687
struct hclgevf_dev *hdev = ae_dev->priv;
16751688

1676-
dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1677-
16781689
if (hdev->default_reset_request)
16791690
hdev->reset_level =
16801691
hclgevf_get_reset_level(&hdev->default_reset_request);
16811692
else
16821693
hdev->reset_level = HNAE3_VF_FUNC_RESET;
16831694

1695+
dev_info(&hdev->pdev->dev, "received reset request from VF enet, reset level is %d\n",
1696+
hdev->reset_level);
1697+
16841698
/* reset of this VF requested */
16851699
set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
16861700
hclgevf_reset_task_schedule(hdev);
@@ -1691,8 +1705,20 @@ static void hclgevf_reset_event(struct pci_dev *pdev,
16911705
static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
16921706
enum hnae3_reset_type rst_type)
16931707
{
1708+
#define HCLGEVF_SUPPORT_RESET_TYPE \
1709+
(BIT(HNAE3_VF_RESET) | BIT(HNAE3_VF_FUNC_RESET) | \
1710+
BIT(HNAE3_VF_PF_FUNC_RESET) | BIT(HNAE3_VF_FULL_RESET) | \
1711+
BIT(HNAE3_FLR_RESET) | BIT(HNAE3_VF_EXP_RESET))
1712+
16941713
struct hclgevf_dev *hdev = ae_dev->priv;
16951714

1715+
if (!(BIT(rst_type) & HCLGEVF_SUPPORT_RESET_TYPE)) {
1716+
/* To prevent reset triggered by hclge_reset_event */
1717+
set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request);
1718+
dev_info(&hdev->pdev->dev, "unsupported reset type %d\n",
1719+
rst_type);
1720+
return;
1721+
}
16961722
set_bit(rst_type, &hdev->default_reset_request);
16971723
}
16981724

@@ -1849,14 +1875,14 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
18491875
*/
18501876
if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
18511877
/* prepare for full reset of stack + pcie interface */
1852-
set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
1878+
hclgevf_set_reset_pending(hdev, HNAE3_VF_FULL_RESET);
18531879

18541880
/* "defer" schedule the reset task again */
18551881
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
18561882
} else {
18571883
hdev->reset_attempts++;
18581884

1859-
set_bit(hdev->reset_level, &hdev->reset_pending);
1885+
hclgevf_set_reset_pending(hdev, hdev->reset_level);
18601886
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
18611887
}
18621888
hclgevf_reset_task_schedule(hdev);
@@ -1979,7 +2005,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
19792005
rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
19802006
dev_info(&hdev->pdev->dev,
19812007
"receive reset interrupt 0x%x!\n", rst_ing_reg);
1982-
set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
2008+
hclgevf_set_reset_pending(hdev, HNAE3_VF_RESET);
19832009
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
19842010
set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
19852011
*clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);

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