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Merge tag 'v6.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner: - New pll-rate for rk3568 - i2s rate improvements for rk3399 - rk3588 syscon clock fixes and removal of overall clock-number from the rk3588 binding header - a prerequisite for later improvements to the rk3588 linked clocks * tag 'v6.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent clk: rockchip: rk3588: use linked clock ID for GATE_LINK clk: rockchip: rk3588: fix indent clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf dt-bindings: clock: rk3588: add missing PCLK_VO1GRF dt-bindings: clock: rk3588: drop CLK_NR_CLKS clk: rockchip: rk3588: fix CLK_NR_CLKS usage clk: rockchip: rk3568: Add PLL rate for 128MHz
2 parents 6613476 + 1361d75 commit 3e76237

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6 files changed

+52
-32
lines changed

6 files changed

+52
-32
lines changed

‎drivers/clk/rockchip/clk-rk3399.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -597,7 +597,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
597597
COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
598598
RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
599599
RK3399_CLKGATE_CON(8), 3, GFLAGS),
600-
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
600+
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
601601
RK3399_CLKSEL_CON(96), 0,
602602
RK3399_CLKGATE_CON(8), 4, GFLAGS,
603603
&rk3399_i2s0_fracmux),
@@ -607,7 +607,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
607607
COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
608608
RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
609609
RK3399_CLKGATE_CON(8), 6, GFLAGS),
610-
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
610+
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
611611
RK3399_CLKSEL_CON(97), 0,
612612
RK3399_CLKGATE_CON(8), 7, GFLAGS,
613613
&rk3399_i2s1_fracmux),
@@ -617,7 +617,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
617617
COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
618618
RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
619619
RK3399_CLKGATE_CON(8), 9, GFLAGS),
620-
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
620+
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
621621
RK3399_CLKSEL_CON(98), 0,
622622
RK3399_CLKGATE_CON(8), 10, GFLAGS,
623623
&rk3399_i2s2_fracmux),

‎drivers/clk/rockchip/clk-rk3568.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
7878
RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
7979
RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
8080
RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
81+
RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0),
8182
RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),
8283
RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
8384
RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),

‎drivers/clk/rockchip/clk-rk3588.c

Lines changed: 28 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
* power, but avoids leaking implementation details into DT or hanging the
3030
* system.
3131
*/
32-
#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
32+
#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
3333
GATE(_id, cname, pname, f, o, b, gf)
3434
#define RK3588_LINKED_CLK CLK_IS_CRITICAL
3535

@@ -1004,7 +1004,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
10041004
GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
10051005
RK3588_CLKGATE_CON(16), 12, GFLAGS),
10061006
GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
1007-
RK3588_CLKGATE_CON(16), 13, GFLAGS),
1007+
RK3588_CLKGATE_CON(16), 13, GFLAGS),
10081008
GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
10091009
RK3588_CLKGATE_CON(19), 3, GFLAGS),
10101010
GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
18511851
RK3588_CLKGATE_CON(56), 0, GFLAGS),
18521852
GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
18531853
RK3588_CLKGATE_CON(56), 1, GFLAGS),
1854-
GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
1855-
RK3588_CLKGATE_CON(55), 10, GFLAGS),
18561854
COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
18571855
RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
18581856
RK3588_CLKGATE_CON(56), 11, GFLAGS),
@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
19981996
RK3588_CLKGATE_CON(60), 9, GFLAGS),
19991997
GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
20001998
RK3588_CLKGATE_CON(60), 10, GFLAGS),
2001-
GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
2002-
RK3588_CLKGATE_CON(59), 12, GFLAGS),
20031999
GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
20042000
RK3588_CLKGATE_CON(59), 14, GFLAGS),
20052001
GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
@@ -2433,40 +2429,45 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
24332429
GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
24342430
RK3588_CLKGATE_CON(68), 2, GFLAGS),
24352431

2436-
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
2437-
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
2438-
GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
2439-
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
2440-
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
2441-
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
2442-
GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
2443-
GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
2444-
GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
2445-
GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
2446-
GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
2447-
GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
2448-
GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
2449-
GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
2450-
GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
2451-
GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
2452-
GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
2453-
GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
2454-
GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
2455-
GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
2432+
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
2433+
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
2434+
GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
2435+
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
2436+
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
2437+
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
2438+
GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
2439+
GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
2440+
GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
2441+
GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
2442+
GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
2443+
GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
2444+
GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
2445+
GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
2446+
GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
2447+
GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
2448+
GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
2449+
GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
2450+
GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
2451+
GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
2452+
GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
2453+
GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
24562454
};
24572455

24582456
static void __init rk3588_clk_init(struct device_node *np)
24592457
{
24602458
struct rockchip_clk_provider *ctx;
2459+
unsigned long clk_nr_clks;
24612460
void __iomem *reg_base;
24622461

2462+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
2463+
ARRAY_SIZE(rk3588_clk_branches)) + 1;
24632464
reg_base = of_iomap(np, 0);
24642465
if (!reg_base) {
24652466
pr_err("%s: could not map cru region\n", __func__);
24662467
return;
24672468
}
24682469

2469-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
2470+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
24702471
if (IS_ERR(ctx)) {
24712472
pr_err("%s: rockchip clk init failed\n", __func__);
24722473
iounmap(reg_base);

‎drivers/clk/rockchip/clk.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
429429
}
430430
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
431431

432+
unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
433+
unsigned int nr_clk)
434+
{
435+
unsigned long max = 0;
436+
unsigned int idx;
437+
438+
for (idx = 0; idx < nr_clk; idx++, list++) {
439+
if (list->id > max)
440+
max = list->id;
441+
if (list->child && list->child->id > max)
442+
max = list->id;
443+
}
444+
445+
return max;
446+
}
447+
EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
448+
432449
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
433450
struct rockchip_clk_branch *list,
434451
unsigned int nr_clk)

‎drivers/clk/rockchip/clk.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -973,6 +973,8 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
973973
void __iomem *base, unsigned long nr_clks);
974974
void rockchip_clk_of_add_provider(struct device_node *np,
975975
struct rockchip_clk_provider *ctx);
976+
unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
977+
unsigned int nr_clk);
976978
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
977979
struct rockchip_clk_branch *list,
978980
unsigned int nr_clk);

‎include/dt-bindings/clock/rockchip,rk3588-cru.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -733,8 +733,7 @@
733733
#define ACLK_AV1_PRE 718
734734
#define PCLK_AV1_PRE 719
735735
#define HCLK_SDIO_PRE 720
736-
737-
#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
736+
#define PCLK_VO1GRF 721
738737

739738
/* scmi-clocks indices */
740739

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