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Merge tag 'v5.9-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Biggest part is the addition of the rk3288 variant of the VMARC SOM and it's Rock Pi N8 icarnation. This brings some arm64 dts-changes with it as the underlying Dalang carrier board is shared by both an arm32 rk3288 SOM and an arm64 rk3399 SOM (Rock Pi N10). Other than that rk3288 gets its ohci node added that only works on the fixed rk3288w variant of the soc and some asorted fixes and improvements for dt-binding-check. * tag 'v5.9-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Add PCIe for RockPI N10 ARM: dts: rockchip: Add HDMI out for RockPI N8/N10 ARM: dts: rockchip: Add USB for RockPI N8/N10 ARM: dts: rockchip: Add usb host0 ohci node for rk3288 ARM: dts: rockchip: Fix VBUS on rk3288-vyasa ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support ARM: dts: rockchip: Add VMARC RK3288 SOM initial support dt-bindings: arm: rockchip: Add Rock Pi N8 binding arm64: dts: rk3399pro: vmarc-som: Move common properties into Carrier arm64: dts: rk3399pro: vmarc-som: Move supply regulators into Carrier arm64: dts: rk3399pro: vmarc-som: Fix sorting nodes, properties ARM: dts: rockchip: dalang-carrier: Move i2c nodes into SOM ARM: dts: rockchip: Add 'arm,pl330-periph-burst' for dmac ARM: dts: rockchip: Add marvell BT irq config ARM: dts: rockchip: rename label and nodename pinctrl subnodes that end with gpio Link: https://lore.kernel.org/r/2472314.kD9Egx1jfM@phil Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 571a9cf + 93ca8ac commit 3ed75c5

20 files changed

+640
-99
lines changed

‎Documentation/devicetree/bindings/arm/rockchip.yaml

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@@ -435,6 +435,12 @@ properties:
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- const: radxa,rockpi4
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- const: rockchip,rk3399
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- description: Radxa ROCK Pi N8
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items:
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- const: radxa,rockpi-n8
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- const: vamrs,rk3288-vmarc-som
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- const: rockchip,rk3288
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- description: Radxa ROCK Pi N10
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items:
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- const: radxa,rockpi-n10

‎arch/arm/boot/dts/Makefile

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@@ -982,6 +982,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk3288-popmetal.dtb \
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rk3288-r89.dtb \
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rk3288-rock2-square.dtb \
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rk3288-rock-pi-n8.dtb \
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rk3288-tinker.dtb \
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rk3288-tinker-s.dtb \
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rk3288-veyron-brain.dtb \

‎arch/arm/boot/dts/rk3036.dtsi

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@@ -67,6 +67,7 @@
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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arm,pl330-periph-burst;
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clocks = <&cru ACLK_DMAC2>;
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clock-names = "apb_pclk";
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};

‎arch/arm/boot/dts/rk322x.dtsi

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@@ -107,6 +107,7 @@
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-periph-burst;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
@@ -520,9 +521,9 @@
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resets = <&cru SRST_TSADC>;
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reset-names = "tsadc-apb";
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pinctrl-names = "init", "default", "sleep";
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pinctrl-0 = <&otp_gpio>;
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pinctrl-0 = <&otp_pin>;
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pinctrl-1 = <&otp_out>;
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pinctrl-2 = <&otp_gpio>;
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pinctrl-2 = <&otp_pin>;
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#thermal-sensor-cells = <0>;
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rockchip,hw-tshut-temp = <95000>;
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status = "disabled";
@@ -1111,7 +1112,7 @@
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};
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tsadc {
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otp_gpio: otp-gpio {
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otp_pin: otp-pin {
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rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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‎arch/arm/boot/dts/rk3288-rock-pi-n8.dts

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@@ -0,0 +1,17 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
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* Copyright (c) 2019 Vamrs Limited
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* Copyright (c) 2019 Amarula Solutions(India)
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*/
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/dts-v1/;
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#include "rk3288.dtsi"
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#include <arm/rockchip-radxa-dalang-carrier.dtsi>
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#include "rk3288-vmarc-som.dtsi"
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/ {
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model = "Radxa ROCK Pi N8";
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compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som",
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"rockchip,rk3288";
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};

‎arch/arm/boot/dts/rk3288-veyron-jaq.dts

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@@ -44,10 +44,25 @@
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};
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};
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&sdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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btmrvl: btmrvl@2 {
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compatible = "marvell,sd8897-bt";
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reg = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
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marvell,wakeup-pin = /bits/ 16 <13>;
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pinctrl-names = "default";
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pinctrl-0 = <&bt_host_wake_l>;
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};
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};
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&sdmmc {
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
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&sdmmc_bus4>;
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};
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‎arch/arm/boot/dts/rk3288-veyron-jerry.dts

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&sdmmc {
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
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&sdmmc_bus4>;
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};
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‎arch/arm/boot/dts/rk3288-veyron-mighty.dts

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};
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&sdmmc {
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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&sdmmc_wp_gpio &sdmmc_bus4>;
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
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&sdmmc_wp_pin &sdmmc_bus4>;
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wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
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/delete-property/ disable-wp;
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};
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&pinctrl {
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sdmmc {
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sdmmc_wp_gpio: sdmmc-wp-gpio {
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sdmmc_wp_pin: sdmmc-wp-pin {
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rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};

‎arch/arm/boot/dts/rk3288-veyron-minnie.dts

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&sdmmc {
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
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&sdmmc_bus4>;
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};
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‎arch/arm/boot/dts/rk3288-veyron-pinky.dts

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};
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sdmmc {
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sdmmc_wp_gpio: sdmmc-wp-gpio {
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sdmmc_wp_pin: sdmmc-wp-pin {
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rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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&sdmmc {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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&sdmmc_wp_gpio &sdmmc_bus4>;
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
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&sdmmc_wp_pin &sdmmc_bus4>;
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wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>;
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};
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