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bebarinobebarino
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Merge tag 'renesas-clk-for-v6.3-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull one more Renesas clk driver update from Geert Uytterhoeven: - Disable R-Car H3 ES1.*, as it was only available to an internal development group and needed a lot of quirks and workarounds. * tag 'renesas-clk-for-v6.3-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
2 parents 65b07ec + b1dec4e commit 3ef6d9b

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5 files changed

+13
-173
lines changed

5 files changed

+13
-173
lines changed

‎drivers/clk/renesas/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ config CLK_RENESAS
2222
select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
2323
select CLK_R8A7792 if ARCH_R8A7792
2424
select CLK_R8A7794 if ARCH_R8A7794
25-
select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951
25+
select CLK_R8A7795 if ARCH_R8A77951
2626
select CLK_R8A77960 if ARCH_R8A77960
2727
select CLK_R8A77961 if ARCH_R8A77961
2828
select CLK_R8A77965 if ARCH_R8A77965

‎drivers/clk/renesas/r8a7795-cpg-mssr.c

Lines changed: 10 additions & 116 deletions
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,6 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
128128
};
129129

130130
static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
131-
DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
132131
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
133132
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
134133
DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
@@ -162,7 +161,6 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
162161
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
163162
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
164163
DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
165-
DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
166164
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
167165
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
168166
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
@@ -187,28 +185,21 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
187185
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
188186
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
189187
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
190-
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
191188
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
192189
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
193190
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
194191
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
195192
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
196-
DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
197193
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
198194
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
199-
DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
200195
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
201196
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
202-
DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
203-
DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
204197
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
205-
DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
206198
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
207199
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
208200
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
209201
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
210202
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
211-
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
212203
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
213204
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
214205
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
@@ -221,7 +212,6 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
221212
DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
222213
DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
223214
DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
224-
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
225215
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
226216
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
227217
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
@@ -350,103 +340,26 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
350340
{ 2, 192, 1, 192, 1, 32, },
351341
};
352342

353-
static const struct soc_device_attribute r8a7795es1[] __initconst = {
343+
static const struct soc_device_attribute r8a7795_denylist[] __initconst = {
354344
{ .soc_id = "r8a7795", .revision = "ES1.*" },
355345
{ /* sentinel */ }
356346
};
357347

358-
359-
/*
360-
* Fixups for R-Car H3 ES1.x
361-
*/
362-
363-
static const unsigned int r8a7795es1_mod_nullify[] __initconst = {
364-
MOD_CLK_ID(326), /* USB-DMAC3-0 */
365-
MOD_CLK_ID(329), /* USB-DMAC3-1 */
366-
MOD_CLK_ID(700), /* EHCI/OHCI3 */
367-
MOD_CLK_ID(705), /* HS-USB-IF3 */
368-
369-
};
370-
371-
static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
372-
{ MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */
373-
{ MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */
374-
{ MOD_CLK_ID(121), R8A7795_CLK_S3D2 }, /* TMU4 */
375-
{ MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */
376-
{ MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */
377-
{ MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
378-
{ MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */
379-
{ MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
380-
{ MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
381-
{ MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */
382-
{ MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */
383-
{ MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */
384-
{ MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */
385-
{ MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */
386-
{ MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */
387-
{ MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */
388-
{ MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */
389-
{ MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */
390-
{ MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */
391-
{ MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */
392-
{ MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */
393-
{ MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */
394-
{ MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */
395-
{ MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */
396-
{ MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */
397-
{ MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */
398-
{ MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */
399-
{ MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */
400-
{ MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */
401-
{ MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */
402-
{ MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */
403-
{ MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */
404-
{ MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */
405-
{ MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */
406-
{ MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */
407-
{ MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */
408-
{ MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */
409-
{ MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */
410-
{ MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */
411-
{ MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */
412-
{ MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */
413-
{ MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */
414-
{ MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */
415-
{ MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */
416-
{ MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */
417-
{ MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */
418-
{ MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */
419-
{ MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */
420-
{ MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */
421-
{ MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */
422-
{ MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */
423-
{ MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */
424-
};
425-
426-
427-
/*
428-
* Fixups for R-Car H3 ES2.x
429-
*/
430-
431-
static const unsigned int r8a7795es2_mod_nullify[] __initconst = {
432-
MOD_CLK_ID(117), /* FDP1-2 */
433-
MOD_CLK_ID(327), /* USB3-IF1 */
434-
MOD_CLK_ID(600), /* FCPVD3 */
435-
MOD_CLK_ID(609), /* FCPVI2 */
436-
MOD_CLK_ID(613), /* FCPF2 */
437-
MOD_CLK_ID(616), /* FCPCI1 */
438-
MOD_CLK_ID(617), /* FCPCI0 */
439-
MOD_CLK_ID(620), /* VSPD3 */
440-
MOD_CLK_ID(629), /* VSPI2 */
441-
MOD_CLK_ID(713), /* CSI21 */
442-
};
443-
444348
static int __init r8a7795_cpg_mssr_init(struct device *dev)
445349
{
446350
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
447351
u32 cpg_mode;
448352
int error;
449353

354+
/*
355+
* We panic here to ensure removed SoCs and clk updates are always in
356+
* sync to avoid overclocking damages. The panic can only be seen with
357+
* commandline args 'earlycon keep_bootcon'. But these SoCs were for
358+
* developers only anyhow.
359+
*/
360+
if (soc_device_match(r8a7795_denylist))
361+
panic("SoC not supported anymore!\n");
362+
450363
error = rcar_rst_read_mode_pins(&cpg_mode);
451364
if (error)
452365
return error;
@@ -457,25 +370,6 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev)
457370
return -EINVAL;
458371
}
459372

460-
if (soc_device_match(r8a7795es1)) {
461-
cpg_core_nullify_range(r8a7795_core_clks,
462-
ARRAY_SIZE(r8a7795_core_clks),
463-
R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);
464-
mssr_mod_nullify(r8a7795_mod_clks,
465-
ARRAY_SIZE(r8a7795_mod_clks),
466-
r8a7795es1_mod_nullify,
467-
ARRAY_SIZE(r8a7795es1_mod_nullify));
468-
mssr_mod_reparent(r8a7795_mod_clks,
469-
ARRAY_SIZE(r8a7795_mod_clks),
470-
r8a7795es1_mod_reparent,
471-
ARRAY_SIZE(r8a7795es1_mod_reparent));
472-
} else {
473-
mssr_mod_nullify(r8a7795_mod_clks,
474-
ARRAY_SIZE(r8a7795_mod_clks),
475-
r8a7795es2_mod_nullify,
476-
ARRAY_SIZE(r8a7795es2_mod_nullify));
477-
}
478-
479373
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
480374
}
481375

‎drivers/clk/renesas/rcar-gen3-cpg.c

Lines changed: 2 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -310,19 +310,10 @@ static unsigned int cpg_clk_extalr __initdata;
310310
static u32 cpg_mode __initdata;
311311
static u32 cpg_quirks __initdata;
312312

313-
#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
314313
#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
315314

316315

317316
static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
318-
{
319-
.soc_id = "r8a7795", .revision = "ES1.0",
320-
.data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
321-
},
322-
{
323-
.soc_id = "r8a7795", .revision = "ES1.*",
324-
.data = (void *)(RCKCR_CKSEL),
325-
},
326317
{
327318
.soc_id = "r8a7796", .revision = "ES1.0",
328319
.data = (void *)(RCKCR_CKSEL),
@@ -355,9 +346,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
355346
* multiplier when cpufreq changes between normal and boost
356347
* modes.
357348
*/
358-
mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
359349
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
360-
base, mult, CPG_PLL0CR, 0);
350+
base, 2, CPG_PLL0CR, 0);
361351

362352
case CLK_TYPE_GEN3_PLL1:
363353
mult = cpg_pll_config->pll1_mult;
@@ -370,9 +360,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
370360
* multiplier when cpufreq changes between normal and boost
371361
* modes.
372362
*/
373-
mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
374363
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
375-
base, mult, CPG_PLL2CR, 2);
364+
base, 2, CPG_PLL2CR, 2);
376365

377366
case CLK_TYPE_GEN3_PLL3:
378367
mult = cpg_pll_config->pll3_mult;
@@ -388,8 +377,6 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
388377
*/
389378
value = readl(base + CPG_PLL4CR);
390379
mult = (((value >> 24) & 0x7f) + 1) * 2;
391-
if (cpg_quirks & PLL_ERRATA)
392-
mult *= 2;
393380
break;
394381

395382
case CLK_TYPE_GEN3_SDH:

‎drivers/clk/renesas/renesas-cpg-mssr.c

Lines changed: 0 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1113,19 +1113,6 @@ static int __init cpg_mssr_init(void)
11131113

11141114
subsys_initcall(cpg_mssr_init);
11151115

1116-
void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
1117-
unsigned int num_core_clks,
1118-
unsigned int first_clk,
1119-
unsigned int last_clk)
1120-
{
1121-
unsigned int i;
1122-
1123-
for (i = 0; i < num_core_clks; i++)
1124-
if (core_clks[i].id >= first_clk &&
1125-
core_clks[i].id <= last_clk)
1126-
core_clks[i].name = NULL;
1127-
}
1128-
11291116
void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
11301117
unsigned int num_mod_clks,
11311118
const unsigned int *clks, unsigned int n)
@@ -1139,19 +1126,5 @@ void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
11391126
}
11401127
}
11411128

1142-
void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
1143-
unsigned int num_mod_clks,
1144-
const struct mssr_mod_reparent *clks,
1145-
unsigned int n)
1146-
{
1147-
unsigned int i, j;
1148-
1149-
for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1150-
if (mod_clks[i].id == clks[j].clk) {
1151-
mod_clks[i].parent = clks[j].parent;
1152-
j++;
1153-
}
1154-
}
1155-
11561129
MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
11571130
MODULE_LICENSE("GPL v2");

‎drivers/clk/renesas/renesas-cpg-mssr.h

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -187,21 +187,7 @@ void __init cpg_mssr_early_init(struct device_node *np,
187187
/*
188188
* Helpers for fixing up clock tables depending on SoC revision
189189
*/
190-
191-
struct mssr_mod_reparent {
192-
unsigned int clk, parent;
193-
};
194-
195-
196-
extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks,
197-
unsigned int num_core_clks,
198-
unsigned int first_clk,
199-
unsigned int last_clk);
200190
extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
201191
unsigned int num_mod_clks,
202192
const unsigned int *clks, unsigned int n);
203-
extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
204-
unsigned int num_mod_clks,
205-
const struct mssr_mod_reparent *clks,
206-
unsigned int n);
207193
#endif

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