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Merge tag 'drm-misc-next-2020-05-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.8: UAPI Changes: Cross-subsystem Changes: * MAINTAINERS: restore alphabetical order; update cirrus driver * Dcomuentation: document visionix, chronteli, ite vendor prefices; update documentation for Chrontel CH7033, IT6505, IVO, BOE, Panasonic, Chunghwa, AUO bindings; convert dw_mipi_dsi.txt to YAML; remove todo item for drm_display_mode.hsync removal; Core Changes: * drm: add devm_drm_dev_alloc() for managed allocations of drm_device; use DRM_MODESET_LOCK_ALL_*() in mode-object code; remove drm_display_mode.hsync; small cleanups of unused variables, compiler warnings and static functions * drm/client: dual-lincensing: GPL-2.0 or MIT * drm/mm: optimize tree searches in rb_hole_addr() Driver Changes: * drm/{many}: use devm_drm_dev_alloc(); don't use drm_device.dev_private * drm/ast: don't double-assign to drm_crtc_funcs.set_config; drop drm_connector_register() * drm/bochs: drop drm_connector_register() * drm/bridge: add support for Chrontel ch7033; fix stack usage with old gccs; return error pointer in drm_panel_bridge_add() * drm/cirrus: Move to tiny * drm/dp_mst: don't use 2nd sideband tx slot; revert "Remove single tx msg restriction" * drm/lima: support runtime PM; * drm/meson: limit modes wrt chipset * drm/panel: add support for Visionox rm69299; fix clock on boe-tv101wum-n16; fix panel type for AUO G101EVN10; add support for Ivo M133NFW4 R0; add support for BOE NV133FHM-N61; add support for AUO G121EAN01.4, G156XTN01.0, G190EAN01 * drm/pl111: improve vexpress init; fix module auto-loading * drm/stm: read number of endpoints from device tree * drm/vboxvideo: use managed PCI functions; drop DRM_MTRR_WC * drm/vkms: fix use-after-free in vkms_gem_create(); enable cursor support by default * fbdev: use boolean values in several drivers * fbdev/controlfb: fix COMPILE_TEST * fbdev/w100fb: fix double-free bug Signed-off-by: Dave Airlie <[email protected]> From: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20200507072503.GA10979@linux-uq9g
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2019,2020 Lubomir Rintel <[email protected]>
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Chrontel CH7033 Video Encoder Device Tree Bindings
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maintainers:
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- Lubomir Rintel <[email protected]>
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properties:
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compatible:
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const: chrontel,ch7033
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reg:
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maxItems: 1
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description: I2C address of the device
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ports:
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type: object
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properties:
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port@0:
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type: object
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description: |
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Video port for RGB input.
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port@1:
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type: object
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description: |
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DVI port, should be connected to a node compatible with the
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dvi-connector binding.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- ports
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additionalProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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vga-dvi-encoder@76 {
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compatible = "chrontel,ch7033";
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reg = <0x76>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&lcd0_rgb_out>;
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};
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&dvi_in>;
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};
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};
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};
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};
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};

Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/ite,it6505.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ITE it6505 Device Tree Bindings
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maintainers:
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- Allen Chen <[email protected]>
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description: |
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The IT6505 is a high-performance DisplayPort 1.1a transmitter,
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fully compliant with DisplayPort 1.1a, HDCP 1.3 specifications.
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The IT6505 supports color depth of up to 36 bits (12 bits/color)
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and ensures robust transmission of high-quality uncompressed video
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content, along with uncompressed and compressed digital audio content.
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Aside from the various video output formats supported, the IT6505
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also encodes and transmits up to 8 channels of I2S digital audio,
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with sampling rate up to 192kHz and sample size up to 24 bits.
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In addition, an S/PDIF input port takes in compressed audio of up to
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192kHz frame rate.
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Each IT6505 chip comes preprogrammed with an unique HDCP key,
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in compliance with the HDCP 1.3 standard so as to provide secure
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transmission of high-definition content. Users of the IT6505 need not
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purchase any HDCP keys or ROMs.
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properties:
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compatible:
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const: ite,it6505
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ovdd-supply:
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maxItems: 1
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description: I/O voltage
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pwr18-supply:
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maxItems: 1
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description: core voltage
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interrupts:
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maxItems: 1
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description: interrupt specifier of INT pin
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reset-gpios:
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maxItems: 1
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description: gpio specifier of RESET pin
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extcon:
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maxItems: 1
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description: extcon specifier for the Power Delivery
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port:
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type: object
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description: A port node pointing to DPI host port node
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required:
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- compatible
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- ovdd-supply
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- pwr18-supply
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- interrupts
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- reset-gpios
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- extcon
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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dp-bridge@5c {
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compatible = "ite,it6505";
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interrupts = <152 IRQ_TYPE_EDGE_FALLING 152 0>;
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reg = <0x5c>;
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pinctrl-names = "default";
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pinctrl-0 = <&it6505_pins>;
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ovdd-supply = <&mt6358_vsim1_reg>;
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pwr18-supply = <&it6505_pp18_reg>;
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reset-gpios = <&pio 179 1>;
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extcon = <&usbc_extcon>;
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port {
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it6505_in: endpoint {
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remote-endpoint = <&dpi_out>;
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};
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};
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};
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};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare MIPI DSI host controller
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maintainers:
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- Philippe CORNU <[email protected]>
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description: |
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This document defines device tree properties for the Synopsys DesignWare MIPI
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DSI host controller. It doesn't constitue a device tree binding specification
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by itself but is meant to be referenced by platform-specific device tree
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bindings.
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When referenced from platform device tree bindings the properties defined in
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this document are defined as follows. The platform device tree bindings are
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responsible for defining whether each property is required or optional.
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allOf:
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- $ref: ../dsi-controller.yaml#
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properties:
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Module clock
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- description: DSI bus clock for either AHB and APB
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- description: Pixel clock for the DPI/RGB input
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minItems: 2
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clock-names:
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items:
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- const: ref
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- const: pclk
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- const: px_clk
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minItems: 2
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resets:
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maxItems: 1
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reset-names:
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const: apb
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ports:
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type: object
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properties:
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port@0:
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type: object
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description: Input node to receive pixel data.
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port@1:
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type: object
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description: DSI output node to panel.
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required:
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- port@0
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- port@1
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required:
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- clock-names
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- clocks
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- ports
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- reg

Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml

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# One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel
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- osddisplays,osd101t2587-53ts
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# Panasonic 10" WUXGA TFT LCD panel
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- panasonic,vvx10f004b00
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# Panasonic 10" WUXGA TFT LCD panel
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- panasonic,vvx10f034n00
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reg:

Documentation/devicetree/bindings/display/panel/panel-simple.yaml

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- auo,g101evn010
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# AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
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- auo,g104sn02
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# AU Optronics Corporation 12.1" (1280x800) TFT LCD panel
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- auo,g121ean01
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# AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel
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- auo,g133han01
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# AU Optronics Corporation 15.6" (1366x768) TFT LCD panel
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- auo,g156xtn01
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# AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel
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- auo,g185han01
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# AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel
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- auo,g190ean01
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# AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel
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- auo,p320hvn03
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# AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel
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- boe,hv070wsa-100
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# BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
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- boe,nv101wxmn51
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# BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel
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- boe,nv133fhm-n61
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# BOE NV140FHM-N49 14.0" FHD a-Si FT panel
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- boe,nv140fhmn49
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# CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel
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# Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
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- chunghwa,claa101wa01a
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# Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
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- chunghwa,claa101wb01
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# Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
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- chunghwa,claa101wb03
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# DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface.
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- dataimage,scf0700c48ggu18
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- hannstar,hsd100pxn1
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# Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel
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- hit,tx23d38vm0caa
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# InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel
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- ivo,m133nwf4-r0
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# Innolux AT043TN24 4.3" WQVGA TFT LCD panel
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- innolux,at043tn24
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# Innolux AT070TN92 7.0" WQVGA TFT LCD panel

Documentation/devicetree/bindings/vendor-prefixes.yaml

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description: ChipOne
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"^chipspark,.*":
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description: ChipSPARK
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"^chrontel,.*":
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description: Chrontel, Inc.
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"^chrp,.*":
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description: Common Hardware Reference Platform
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"^chunghwa,.*":
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description: Infineon Technologies
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"^inforce,.*":
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description: Inforce Computing
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"^ivo,.*":
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description: InfoVision Optoelectronics Kunshan Co. Ltd.
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"^ingenic,.*":
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description: Ingenic Semiconductor
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"^innolux,.*":
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"^issi,.*":
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description: Integrated Silicon Solutions Inc.
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"^ite,.*":
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description: ITE Tech, Inc.
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description: ITE Tech. Inc.
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"^itead,.*":
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description: ITEAD Intelligent Systems Co.Ltd
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"^iwave,.*":
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description: Tronsmart
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"^truly,.*":
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description: Truly Semiconductors Limited
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"^visionox,.*":
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description: Visionox
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"^tsd,.*":
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description: Theobroma Systems Design und Consulting GmbH
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"^tyan,.*":

Documentation/gpu/todo.rst

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Level: Starter
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Remove drm_display_mode.hsync
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-----------------------------
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We have drm_mode_hsync() to calculate this from hsync_start/end, since drivers
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shouldn't/don't use this, remove this member to avoid any temptations to use it
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in the future. If there is any debug code using drm_display_mode.hsync, convert
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it to use drm_mode_hsync() instead.
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Contact: Sean Paul
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Level: Starter
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connector register/unregister fixes
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-----------------------------------
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MAINTAINERS

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S: Obsolete
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W: https://www.kraxel.org/blog/2014/10/qemu-using-cirrus-considered-harmful/
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T: git git://anongit.freedesktop.org/drm/drm-misc
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F: drivers/gpu/drm/cirrus/
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F: drivers/gpu/drm/tiny/cirrus.c
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DRM DRIVER FOR QXL VIRTUAL GPU
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M: Dave Airlie <[email protected]>

drivers/gpu/drm/Kconfig

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source "drivers/gpu/drm/mgag200/Kconfig"
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source "drivers/gpu/drm/cirrus/Kconfig"
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source "drivers/gpu/drm/armada/Kconfig"
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source "drivers/gpu/drm/atmel-hlcdc/Kconfig"

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