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| 1 | +# SPDX-License-Identifier: GPL-2.0-only |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: SPI NOR flash ST M25Pxx (and similar) serial flash chips |
| 8 | + |
| 9 | +maintainers: |
| 10 | + |
| 11 | + |
| 12 | +properties: |
| 13 | + compatible: |
| 14 | + oneOf: |
| 15 | + - items: |
| 16 | + - pattern: "^((((micron|spansion|st),)?\ |
| 17 | + (m25p(40|80|16|32|64|128)|\ |
| 18 | + n25q(32b|064|128a11|128a13|256a|512a|164k)))|\ |
| 19 | + atmel,at25df(321a|641|081a)|\ |
| 20 | + everspin,mr25h(10|40|128|256)|\ |
| 21 | + (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\ |
| 22 | + (mxicy|macronix),mx25u(4033|4035)|\ |
| 23 | + (spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\ |
| 24 | + (sst|microchip),sst25vf(016b|032b|040b)|\ |
| 25 | + (sst,)?sst26wf016b|\ |
| 26 | + (sst,)?sst25wf(040b|080)|\ |
| 27 | + winbond,w25x(80|32)|\ |
| 28 | + (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$" |
| 29 | + - const: jedec,spi-nor |
| 30 | + - items: |
| 31 | + - enum: |
| 32 | + - issi,is25lp016d |
| 33 | + - micron,mt25qu02g |
| 34 | + - mxicy,mx25r1635f |
| 35 | + - mxicy,mx25u6435f |
| 36 | + - mxicy,mx25v8035f |
| 37 | + - spansion,s25sl12801 |
| 38 | + - spansion,s25fs512s |
| 39 | + - const: jedec,spi-nor |
| 40 | + - const: jedec,spi-nor |
| 41 | + description: |
| 42 | + Must also include "jedec,spi-nor" for any SPI NOR flash that can be |
| 43 | + identified by the JEDEC READ ID opcode (0x9F). |
| 44 | + |
| 45 | + reg: |
| 46 | + maxItems: 1 |
| 47 | + |
| 48 | + spi-max-frequency: true |
| 49 | + spi-rx-bus-width: true |
| 50 | + spi-tx-bus-width: true |
| 51 | + |
| 52 | + m25p,fast-read: |
| 53 | + type: boolean |
| 54 | + description: |
| 55 | + Use the "fast read" opcode to read data from the chip instead of the usual |
| 56 | + "read" opcode. This opcode is not supported by all chips and support for |
| 57 | + it can not be detected at runtime. Refer to your chips' datasheet to check |
| 58 | + if this is supported by your chip. |
| 59 | + |
| 60 | + broken-flash-reset: |
| 61 | + type: boolean |
| 62 | + description: |
| 63 | + Some flash devices utilize stateful addressing modes (e.g., for 32-bit |
| 64 | + addressing) which need to be managed carefully by a system. Because these |
| 65 | + sorts of flash don't have a standardized software reset command, and |
| 66 | + because some systems don't toggle the flash RESET# pin upon system reset |
| 67 | + (if the pin even exists at all), there are systems which cannot reboot |
| 68 | + properly if the flash is left in the "wrong" state. This boolean flag can |
| 69 | + be used on such systems, to denote the absence of a reliable reset |
| 70 | + mechanism. |
| 71 | + |
| 72 | + label: true |
| 73 | + |
| 74 | + partitions: |
| 75 | + type: object |
| 76 | + |
| 77 | + '#address-cells': true |
| 78 | + '#size-cells': true |
| 79 | + |
| 80 | +patternProperties: |
| 81 | + # Note: use 'partitions' node for new users |
| 82 | + '^partition@': |
| 83 | + type: object |
| 84 | + |
| 85 | +additionalProperties: false |
| 86 | + |
| 87 | +examples: |
| 88 | + - | |
| 89 | + spi { |
| 90 | + #address-cells = <1>; |
| 91 | + #size-cells = <0>; |
| 92 | +
|
| 93 | + flash@0 { |
| 94 | + #address-cells = <1>; |
| 95 | + #size-cells = <1>; |
| 96 | + compatible = "spansion,m25p80", "jedec,spi-nor"; |
| 97 | + reg = <0>; |
| 98 | + spi-max-frequency = <40000000>; |
| 99 | + m25p,fast-read; |
| 100 | + }; |
| 101 | + }; |
| 102 | +... |
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