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perf vendor events intel: Refresh sapphirerapids metrics and events
Update the sapphirerapids metrics and events using the new tooling from: https://github.com/intel/perfmon The metrics are unchanged but the formulas differ due to parentheses, use of exponents and removal of redundant operations like "* 1". The order of metrics varies as TMA metrics are first converted and then removed if perfmon versions are found. The events are updated to 1.09, in particular uncore, with fixes to uncore events and improved descriptions. The formatting changes increase consistency across the json files. Signed-off-by: Ian Rogers <[email protected]> Acked-by: Kan Liang <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Caleb Biggers <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: John Garry <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Perry Taylor <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Xing Zhengjun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
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‎tools/perf/pmu-events/arch/x86/mapfile.csv

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@@ -21,7 +21,7 @@ GenuineIntel-6-A[AC],v1.00,meteorlake,core
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GenuineIntel-6-1[AEF],v3,nehalemep,core
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GenuineIntel-6-2E,v3,nehalemex,core
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GenuineIntel-6-2A,v17,sandybridge,core
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GenuineIntel-6-8F,v1.06,sapphirerapids,core
24+
GenuineIntel-6-8F,v1.09,sapphirerapids,core
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GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core
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GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core
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GenuineIntel-6-55-[01234],v1.28,skylakex,core

‎tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json

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‎tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json

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@@ -1,222 +1,159 @@
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[
22
{
33
"BriefDescription": "ARITH.FPDIV_ACTIVE",
4-
"CollectPEBSRecord": "2",
5-
"Counter": "0,1,2,3,4,5,6,7",
64
"CounterMask": "1",
75
"EventCode": "0xb0",
86
"EventName": "ARITH.FPDIV_ACTIVE",
9-
"PEBScounters": "0,1,2,3,4,5,6,7",
107
"SampleAfterValue": "1000003",
11-
"Speculative": "1",
128
"UMask": "0x1"
139
},
1410
{
1511
"BriefDescription": "Counts all microcode FP assists.",
16-
"CollectPEBSRecord": "2",
17-
"Counter": "0,1,2,3,4,5,6,7",
1812
"EventCode": "0xc1",
1913
"EventName": "ASSISTS.FP",
20-
"PEBScounters": "0,1,2,3,4,5,6,7",
2114
"PublicDescription": "Counts all microcode Floating Point assists.",
2215
"SampleAfterValue": "100003",
23-
"Speculative": "1",
2416
"UMask": "0x2"
2517
},
2618
{
2719
"BriefDescription": "ASSISTS.SSE_AVX_MIX",
28-
"CollectPEBSRecord": "2",
29-
"Counter": "0,1,2,3,4,5,6,7",
3020
"EventCode": "0xc1",
3121
"EventName": "ASSISTS.SSE_AVX_MIX",
32-
"PEBScounters": "0,1,2,3,4,5,6,7",
3322
"SampleAfterValue": "1000003",
34-
"Speculative": "1",
3523
"UMask": "0x10"
3624
},
3725
{
3826
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
39-
"CollectPEBSRecord": "2",
40-
"Counter": "0,1,2,3,4,5,6,7",
4127
"EventCode": "0xb3",
4228
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
43-
"PEBScounters": "0,1,2,3,4,5,6,7",
4429
"SampleAfterValue": "2000003",
45-
"Speculative": "1",
4630
"UMask": "0x1"
4731
},
4832
{
4933
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
50-
"CollectPEBSRecord": "2",
51-
"Counter": "0,1,2,3,4,5,6,7",
5234
"EventCode": "0xb3",
5335
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
54-
"PEBScounters": "0,1,2,3,4,5,6,7",
5536
"SampleAfterValue": "2000003",
56-
"Speculative": "1",
5737
"UMask": "0x2"
5838
},
5939
{
6040
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
61-
"CollectPEBSRecord": "2",
62-
"Counter": "0,1,2,3,4,5,6,7",
6341
"EventCode": "0xb3",
6442
"EventName": "FP_ARITH_DISPATCHED.PORT_5",
65-
"PEBScounters": "0,1,2,3,4,5,6,7",
6643
"SampleAfterValue": "2000003",
67-
"Speculative": "1",
6844
"UMask": "0x4"
6945
},
7046
{
7147
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
72-
"CollectPEBSRecord": "2",
73-
"Counter": "0,1,2,3,4,5,6,7",
7448
"EventCode": "0xc7",
7549
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
76-
"PEBScounters": "0,1,2,3,4,5,6,7",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
83-
"CollectPEBSRecord": "2",
84-
"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
87-
"PEBScounters": "0,1,2,3,4,5,6,7",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
8959
"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
94-
"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
98-
"PEBScounters": "0,1,2,3,4,5,6,7",
9966
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
10370
{
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"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
105-
"CollectPEBSRecord": "2",
106-
"Counter": "0,1,2,3,4,5,6,7",
10772
"EventCode": "0xc7",
10873
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
109-
"PEBScounters": "0,1,2,3,4,5,6,7",
11074
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
11175
"SampleAfterValue": "100003",
11276
"UMask": "0x20"
11377
},
11478
{
11579
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
116-
"CollectPEBSRecord": "2",
117-
"Counter": "0,1,2,3,4,5,6,7",
11880
"EventCode": "0xc7",
11981
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
120-
"PEBScounters": "0,1,2,3,4,5,6,7",
12182
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
12283
"SampleAfterValue": "100003",
12384
"UMask": "0x40"
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},
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{
12687
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
127-
"CollectPEBSRecord": "2",
128-
"Counter": "0,1,2,3,4,5,6,7",
12988
"EventCode": "0xc7",
13089
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
131-
"PEBScounters": "0,1,2,3,4,5,6,7",
13290
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
13391
"SampleAfterValue": "100003",
13492
"UMask": "0x80"
13593
},
13694
{
13795
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
138-
"CollectPEBSRecord": "2",
139-
"Counter": "0,1,2,3,4,5,6,7",
14096
"EventCode": "0xc7",
14197
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
142-
"PEBScounters": "0,1,2,3,4,5,6,7",
14398
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
14499
"SampleAfterValue": "100003",
145100
"UMask": "0x1"
146101
},
147102
{
148103
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
149-
"CollectPEBSRecord": "2",
150-
"Counter": "0,1,2,3,4,5,6,7",
151104
"EventCode": "0xc7",
152105
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
153-
"PEBScounters": "0,1,2,3,4,5,6,7",
154106
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
155107
"SampleAfterValue": "100003",
156108
"UMask": "0x2"
157109
},
158110
{
159111
"BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
160-
"Counter": "0,1,2,3,4,5,6,7",
161112
"EventCode": "0xcf",
162113
"EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
163-
"PEBScounters": "0,1,2,3,4,5,6,7",
164114
"SampleAfterValue": "100003",
165115
"UMask": "0x4"
166116
},
167117
{
168118
"BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
169-
"Counter": "0,1,2,3,4,5,6,7",
170119
"EventCode": "0xcf",
171120
"EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
172-
"PEBScounters": "0,1,2,3,4,5,6,7",
173121
"SampleAfterValue": "100003",
174122
"UMask": "0x8"
175123
},
176124
{
177125
"BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
178-
"CollectPEBSRecord": "2",
179-
"Counter": "0,1,2,3,4,5,6,7",
180126
"EventCode": "0xcf",
181127
"EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
182-
"PEBScounters": "0,1,2,3,4,5,6,7",
183128
"SampleAfterValue": "100003",
184129
"UMask": "0x10"
185130
},
186131
{
187132
"BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
188-
"Counter": "0,1,2,3,4,5,6,7",
189133
"EventCode": "0xcf",
190134
"EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
191-
"PEBScounters": "0,1,2,3,4,5,6,7",
192135
"SampleAfterValue": "100003",
193136
"UMask": "0x2"
194137
},
195138
{
196139
"BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
197-
"Counter": "0,1,2,3,4,5,6,7",
198140
"EventCode": "0xcf",
199141
"EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
200-
"PEBScounters": "0,1,2,3,4,5,6,7",
201142
"PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
202143
"SampleAfterValue": "100003",
203144
"UMask": "0x3"
204145
},
205146
{
206147
"BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
207-
"Counter": "0,1,2,3,4,5,6,7",
208148
"EventCode": "0xcf",
209149
"EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
210-
"PEBScounters": "0,1,2,3,4,5,6,7",
211150
"SampleAfterValue": "100003",
212151
"UMask": "0x1"
213152
},
214153
{
215154
"BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
216-
"Counter": "0,1,2,3,4,5,6,7",
217155
"EventCode": "0xcf",
218156
"EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
219-
"PEBScounters": "0,1,2,3,4,5,6,7",
220157
"PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
221158
"SampleAfterValue": "100003",
222159
"UMask": "0x1c"

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