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jnikulajnikula
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drm/i915: pass dev_priv to _MMIO_PIPE2, _MMIO_TRANS2, _MMIO_CURSOR2
Pass the dev_priv parameter to the low-level helpers, and move the implicit dev_priv usage one level higher. sed -i "s/\(_MMIO_PIPE2(\|_MMIO_TRANS2(\|_MMIO_CURSOR2(\)/\1dev_priv, /" \ $(git ls-files drivers/gpu/drm/i915) Name the parameter "display", as the generics allow it to be display already. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/3a865664898586ff6cb8e74eab3d1f36eafc0557.1713890614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
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‎drivers/gpu/drm/i915/display/intel_color_regs.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -228,12 +228,12 @@
228228
#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */
229229
#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */
230230

231-
#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00)
232-
#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)
233-
#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10)
234-
#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)
235-
#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20)
236-
#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)
231+
#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00)
232+
#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)
233+
#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)
234+
#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)
235+
#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)
236+
#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)
237237

238238
/* pipe CSC & degamma/gamma LUTs on CHV */
239239
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)

‎drivers/gpu/drm/i915/display/intel_display_reg_defs.h

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -36,14 +36,14 @@
3636
* Device info offset array based helpers for groups of registers with unevenly
3737
* spaced base offsets.
3838
*/
39-
#define _MMIO_PIPE2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->pipe_offsets[(pipe)] - \
40-
DISPLAY_INFO(dev_priv)->pipe_offsets[PIPE_A] + \
41-
DISPLAY_MMIO_BASE(dev_priv) + (reg))
42-
#define _MMIO_TRANS2(tran, reg) _MMIO(DISPLAY_INFO(dev_priv)->trans_offsets[(tran)] - \
43-
DISPLAY_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + \
44-
DISPLAY_MMIO_BASE(dev_priv) + (reg))
45-
#define _MMIO_CURSOR2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->cursor_offsets[(pipe)] - \
46-
DISPLAY_INFO(dev_priv)->cursor_offsets[PIPE_A] + \
47-
DISPLAY_MMIO_BASE(dev_priv) + (reg))
39+
#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \
40+
DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
41+
DISPLAY_MMIO_BASE(display) + (reg))
42+
#define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \
43+
DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \
44+
DISPLAY_MMIO_BASE(display) + (reg))
45+
#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \
46+
DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
47+
DISPLAY_MMIO_BASE(display) + (reg))
4848

4949
#endif /* __INTEL_DISPLAY_REG_DEFS_H__ */

‎drivers/gpu/drm/i915/display/intel_psr_regs.h

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
#include "intel_display_reg_defs.h"
1010
#include "intel_dp_aux_regs.h"
1111

12-
#define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A)
12+
#define TRANS_EXITLINE(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)
1313
#define EXITLINE_ENABLE REG_BIT(31)
1414
#define EXITLINE_MASK REG_GENMASK(12, 0)
1515
#define EXITLINE_SHIFT 0
@@ -23,7 +23,7 @@
2323
#define HSW_SRD_CTL _MMIO(0x64800)
2424
#define _SRD_CTL_A 0x60800
2525
#define _SRD_CTL_EDP 0x6f800
26-
#define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A)
26+
#define EDP_PSR_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)
2727
#define EDP_PSR_ENABLE REG_BIT(31)
2828
#define BDW_PSR_SINGLE_FRAME REG_BIT(30)
2929
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */
@@ -66,8 +66,8 @@
6666
#define EDP_PSR_IIR _MMIO(0x64838)
6767
#define _PSR_IMR_A 0x60814
6868
#define _PSR_IIR_A 0x60818
69-
#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
70-
#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
69+
#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
70+
#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
7171
#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
7272
0 : ((trans) - TRANSCODER_A + 1) * 8)
7373
#define TGL_PSR_MASK REG_GENMASK(2, 0)
@@ -86,7 +86,7 @@
8686
#define HSW_SRD_AUX_CTL _MMIO(0x64810)
8787
#define _SRD_AUX_CTL_A 0x60810
8888
#define _SRD_AUX_CTL_EDP 0x6f810
89-
#define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(tran, _SRD_AUX_CTL_A)
89+
#define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
9090
#define EDP_PSR_AUX_CTL_TIME_OUT_MASK DP_AUX_CH_CTL_TIME_OUT_MASK
9191
#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
9292
#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK DP_AUX_CH_CTL_PRECHARGE_2US_MASK
@@ -96,12 +96,12 @@
9696
#define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */
9797
#define _SRD_AUX_DATA_A 0x60814
9898
#define _SRD_AUX_DATA_EDP 0x6f814
99-
#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
99+
#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
100100

101101
#define HSW_SRD_STATUS _MMIO(0x64840)
102102
#define _SRD_STATUS_A 0x60840
103103
#define _SRD_STATUS_EDP 0x6f840
104-
#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A)
104+
#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)
105105
#define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29)
106106
#define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)
107107
#define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)
@@ -126,14 +126,14 @@
126126
#define HSW_SRD_PERF_CNT _MMIO(0x64844)
127127
#define _SRD_PERF_CNT_A 0x60844
128128
#define _SRD_PERF_CNT_EDP 0x6f844
129-
#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
129+
#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)
130130
#define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0)
131131

132132
/* PSR_MASK on SKL+ */
133133
#define HSW_SRD_DEBUG _MMIO(0x64860)
134134
#define _SRD_DEBUG_A 0x60860
135135
#define _SRD_DEBUG_EDP 0x6f860
136-
#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A)
136+
#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)
137137
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28)
138138
#define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27)
139139
#define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26)
@@ -153,7 +153,7 @@
153153

154154
#define _PSR2_CTL_A 0x60900
155155
#define _PSR2_CTL_EDP 0x6f900
156-
#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
156+
#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)
157157
#define EDP_PSR2_ENABLE REG_BIT(31)
158158
#define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */
159159
#define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28)
@@ -195,7 +195,7 @@
195195
#define _PSR_EVENT_TRANS_C 0x62848
196196
#define _PSR_EVENT_TRANS_D 0x63848
197197
#define _PSR_EVENT_TRANS_EDP 0x6f848
198-
#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
198+
#define PSR_EVENT(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)
199199
#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17)
200200
#define PSR_EVENT_PSR2_DISABLED REG_BIT(16)
201201
#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15)
@@ -215,21 +215,21 @@
215215

216216
#define _PSR2_STATUS_A 0x60940
217217
#define _PSR2_STATUS_EDP 0x6f940
218-
#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
218+
#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)
219219
#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
220220
#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
221221

222222
#define _PSR2_SU_STATUS_A 0x60914
223223
#define _PSR2_SU_STATUS_EDP 0x6f914
224-
#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
224+
#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
225225
#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
226226
#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
227227
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
228228
#define PSR2_SU_STATUS_FRAMES 8
229229

230230
#define _PSR2_MAN_TRK_CTL_A 0x60910
231231
#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
232-
#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
232+
#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)
233233
#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
234234
#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
235235
#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
@@ -249,7 +249,7 @@
249249
/* PSR2 Early transport */
250250
#define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
251251

252-
#define PIPE_SRCSZ_ERLY_TPT(trans) _MMIO_TRANS2(trans, _PIPE_SRCSZ_ERLY_TPT_A)
252+
#define PIPE_SRCSZ_ERLY_TPT(trans) _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
253253

254254
#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
255255
#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
@@ -297,7 +297,7 @@
297297
_SEL_FETCH_PLANE_BASE_1_A)
298298

299299
#define _ALPM_CTL_A 0x60950
300-
#define ALPM_CTL(tran) _MMIO_TRANS2(tran, _ALPM_CTL_A)
300+
#define ALPM_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
301301
#define ALPM_CTL_ALPM_ENABLE REG_BIT(31)
302302
#define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30)
303303
#define ALPM_CTL_LOBF_ENABLE REG_BIT(29)
@@ -321,7 +321,7 @@
321321
#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
322322

323323
#define _ALPM_CTL2_A 0x60954
324-
#define ALPM_CTL2(tran) _MMIO_TRANS2(tran, _ALPM_CTL2_A)
324+
#define ALPM_CTL2(tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
325325
#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24)
326326
#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
327327
#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16)
@@ -335,7 +335,7 @@
335335
#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)
336336

337337
#define _PORT_ALPM_CTL_A 0x16fa2c
338-
#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_CTL_A)
338+
#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
339339
#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31)
340340
#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20)
341341
#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)
@@ -345,7 +345,7 @@
345345
#define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val)
346346

347347
#define _PORT_ALPM_LFPS_CTL_A 0x16fa30
348-
#define PORT_ALPM_LFPS_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_LFPS_CTL_A)
348+
#define PORT_ALPM_LFPS_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)
349349
#define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31)
350350
#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24)
351351
#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7

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