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ahduyckkuba-moo
ahduyck
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eth: fbnic: Implement Tx queue alloc/start/stop/free
Implement basic management operations for Tx queues. Allocate memory for submission and completion rings. Learn how to start the queues, stop them, and wait for HW to be idle. We call HW rings "descriptor rings" (stored in ring->desc), and SW context rings "buffer rings" (stored in ring->*_buf union). This is the first patch which actually touches CSRs so add CSR helpers. No actual datapath / packet handling here, yet. Signed-off-by: Alexander Duyck <[email protected]> Link: https://patch.msgid.link/172079938724.1778861.8329677776612865169.stgit@ahduyck-xeon-server.home.arpa Signed-off-by: Jakub Kicinski <[email protected]>
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6 files changed

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‎drivers/net/ethernet/meta/fbnic/fbnic_csr.h

Lines changed: 62 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -61,10 +61,18 @@
6161
#define FBNIC_INTR_CQ_REARM_INTR_RELOAD CSR_BIT(30)
6262
#define FBNIC_INTR_CQ_REARM_INTR_UNMASK CSR_BIT(31)
6363

64+
#define FBNIC_INTR_RCQ_TIMEOUT(n) \
65+
(0x00401 + 4 * (n)) /* 0x01004 + 16*n */
66+
#define FBNIC_INTR_RCQ_TIMEOUT_CNT 256
67+
#define FBNIC_INTR_TCQ_TIMEOUT(n) \
68+
(0x00402 + 4 * (n)) /* 0x01008 + 16*n */
69+
#define FBNIC_INTR_TCQ_TIMEOUT_CNT 256
6470
#define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */
6571

6672
/* Global QM Tx registers */
6773
#define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */
74+
#define FBNIC_QM_TWQ_IDLE(n) (0x00800 + (n)) /* 0x02000 + 4*n */
75+
#define FBNIC_QM_TWQ_IDLE_CNT 8
6876
#define FBNIC_QM_TWQ_DEFAULT_META_L 0x00818 /* 0x02060 */
6977
#define FBNIC_QM_TWQ_DEFAULT_META_H 0x00819 /* 0x02064 */
7078

@@ -86,10 +94,16 @@ enum {
8694
#define FBNIC_QM_TQS_MTU_CTL0 0x0081d /* 0x02074 */
8795
#define FBNIC_QM_TQS_MTU_CTL1 0x0081e /* 0x02078 */
8896
#define FBNIC_QM_TQS_MTU_CTL1_BULK CSR_GENMASK(13, 0)
97+
#define FBNIC_QM_TCQ_IDLE(n) (0x00821 + (n)) /* 0x02084 + 4*n */
98+
#define FBNIC_QM_TCQ_IDLE_CNT 4
8999
#define FBNIC_QM_TCQ_CTL0 0x0082d /* 0x020b4 */
90100
#define FBNIC_QM_TCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)
91101
#define FBNIC_QM_TCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16)
102+
#define FBNIC_QM_TQS_IDLE(n) (0x00830 + (n)) /* 0x020c0 + 4*n */
103+
#define FBNIC_QM_TQS_IDLE_CNT 8
92104
#define FBNIC_QM_TQS_EDT_TS_RANGE 0x00849 /* 0x2124 */
105+
#define FBNIC_QM_TDE_IDLE(n) (0x00853 + (n)) /* 0x0214c + 4*n */
106+
#define FBNIC_QM_TDE_IDLE_CNT 8
93107
#define FBNIC_QM_TNI_TDF_CTL 0x0086c /* 0x021b0 */
94108
#define FBNIC_QM_TNI_TDF_CTL_MRRS CSR_GENMASK(1, 0)
95109
#define FBNIC_QM_TNI_TDF_CTL_CLS CSR_GENMASK(3, 2)
@@ -110,9 +124,15 @@ enum {
110124

111125
/* Global QM Rx registers */
112126
#define FBNIC_CSR_START_QM_RX 0x00c00 /* CSR section delimiter */
127+
#define FBNIC_QM_RCQ_IDLE(n) (0x00c00 + (n)) /* 0x03000 + 0x4*n */
128+
#define FBNIC_QM_RCQ_IDLE_CNT 4
113129
#define FBNIC_QM_RCQ_CTL0 0x00c0c /* 0x03030 */
114130
#define FBNIC_QM_RCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)
115131
#define FBNIC_QM_RCQ_CTL0_TICK_CYCLES CSR_GENMASK(26, 16)
132+
#define FBNIC_QM_HPQ_IDLE(n) (0x00c0f + (n)) /* 0x0303c + 0x4*n */
133+
#define FBNIC_QM_HPQ_IDLE_CNT 4
134+
#define FBNIC_QM_PPQ_IDLE(n) (0x00c13 + (n)) /* 0x0304c + 0x4*n */
135+
#define FBNIC_QM_PPQ_IDLE_CNT 4
116136
#define FBNIC_QM_RNI_RBP_CTL 0x00c2d /* 0x030b4 */
117137
#define FBNIC_QM_RNI_RBP_CTL_MRRS CSR_GENMASK(1, 0)
118138
#define FBNIC_QM_RNI_RBP_CTL_CLS CSR_GENMASK(3, 2)
@@ -219,6 +239,8 @@ enum {
219239
/* TMI registers */
220240
#define FBNIC_CSR_START_TMI 0x04400 /* CSR section delimiter */
221241
#define FBNIC_TMI_SOP_PROT_CTRL 0x04400 /* 0x11000 */
242+
#define FBNIC_TMI_DROP_CTRL 0x04401 /* 0x11004 */
243+
#define FBNIC_TMI_DROP_CTRL_EN CSR_BIT(0)
222244
#define FBNIC_CSR_END_TMI 0x0443f /* CSR section delimiter */
223245
/* Rx Buffer Registers */
224246
#define FBNIC_CSR_START_RXB 0x08000 /* CSR section delimiter */
@@ -382,22 +404,52 @@ enum {
382404
#define FBNIC_QUEUE_TWQ1_CTL 0x001 /* 0x004 */
383405
#define FBNIC_QUEUE_TWQ_CTL_RESET CSR_BIT(0)
384406
#define FBNIC_QUEUE_TWQ_CTL_ENABLE CSR_BIT(1)
385-
#define FBNIC_QUEUE_TWQ_CTL_PREFETCH_DISABLE CSR_BIT(2)
386-
#define FBNIC_QUEUE_TWQ_CTL_TXB_FIFO_SEL_MASK CSR_GENMASK(30, 29)
387-
enum {
388-
FBNIC_QUEUE_TWQ_CTL_TXB_SHARED = 0,
389-
FBNIC_QUEUE_TWQ_CTL_TXB_EI_DATA = 1,
390-
FBNIC_QUEUE_TWQ_CTL_TXB_EI_CTL = 2,
391-
};
392-
393-
#define FBNIC_QUEUE_TWQ_CTL_AGGR_MODE CSR_BIT(31)
394-
395407
#define FBNIC_QUEUE_TWQ0_TAIL 0x002 /* 0x008 */
396408
#define FBNIC_QUEUE_TWQ1_TAIL 0x003 /* 0x00c */
397409

410+
#define FBNIC_QUEUE_TWQ0_SIZE 0x00a /* 0x028 */
411+
#define FBNIC_QUEUE_TWQ1_SIZE 0x00b /* 0x02c */
412+
#define FBNIC_QUEUE_TWQ_SIZE_MASK CSR_GENMASK(3, 0)
413+
414+
#define FBNIC_QUEUE_TWQ0_BAL 0x020 /* 0x080 */
415+
#define FBNIC_QUEUE_BAL_MASK CSR_GENMASK(31, 7)
416+
#define FBNIC_QUEUE_TWQ0_BAH 0x021 /* 0x084 */
417+
#define FBNIC_QUEUE_TWQ1_BAL 0x022 /* 0x088 */
418+
#define FBNIC_QUEUE_TWQ1_BAH 0x023 /* 0x08c */
419+
398420
/* Tx Completion Queue Registers */
421+
#define FBNIC_QUEUE_TCQ_CTL 0x080 /* 0x200 */
422+
#define FBNIC_QUEUE_TCQ_CTL_RESET CSR_BIT(0)
423+
#define FBNIC_QUEUE_TCQ_CTL_ENABLE CSR_BIT(1)
424+
399425
#define FBNIC_QUEUE_TCQ_HEAD 0x081 /* 0x204 */
400426

427+
#define FBNIC_QUEUE_TCQ_SIZE 0x084 /* 0x210 */
428+
#define FBNIC_QUEUE_TCQ_SIZE_MASK CSR_GENMASK(3, 0)
429+
430+
#define FBNIC_QUEUE_TCQ_BAL 0x0a0 /* 0x280 */
431+
#define FBNIC_QUEUE_TCQ_BAH 0x0a1 /* 0x284 */
432+
433+
/* Tx Interrupt Manager Registers */
434+
#define FBNIC_QUEUE_TIM_CTL 0x0c0 /* 0x300 */
435+
#define FBNIC_QUEUE_TIM_CTL_MSIX_MASK CSR_GENMASK(7, 0)
436+
437+
#define FBNIC_QUEUE_TIM_THRESHOLD 0x0c1 /* 0x304 */
438+
#define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK CSR_GENMASK(14, 0)
439+
440+
#define FBNIC_QUEUE_TIM_CLEAR 0x0c2 /* 0x308 */
441+
#define FBNIC_QUEUE_TIM_CLEAR_MASK CSR_BIT(0)
442+
#define FBNIC_QUEUE_TIM_SET 0x0c3 /* 0x30c */
443+
#define FBNIC_QUEUE_TIM_SET_MASK CSR_BIT(0)
444+
#define FBNIC_QUEUE_TIM_MASK 0x0c4 /* 0x310 */
445+
#define FBNIC_QUEUE_TIM_MASK_MASK CSR_BIT(0)
446+
447+
#define FBNIC_QUEUE_TIM_TIMER 0x0c5 /* 0x314 */
448+
449+
#define FBNIC_QUEUE_TIM_COUNTS 0x0c6 /* 0x318 */
450+
#define FBNIC_QUEUE_TIM_COUNTS_CNT1_MASK CSR_GENMASK(30, 16)
451+
#define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK CSR_GENMASK(14, 0)
452+
401453
/* Rx Completion Queue Registers */
402454
#define FBNIC_QUEUE_RCQ_HEAD 0x201 /* 0x804 */
403455

‎drivers/net/ethernet/meta/fbnic/fbnic_netdev.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,10 @@ int __fbnic_open(struct fbnic_net *fbn)
1717
if (err)
1818
return err;
1919

20+
err = fbnic_alloc_resources(fbn);
21+
if (err)
22+
goto free_napi_vectors;
23+
2024
err = netif_set_real_num_tx_queues(fbn->netdev,
2125
fbn->num_tx_queues);
2226
if (err)
@@ -29,6 +33,8 @@ int __fbnic_open(struct fbnic_net *fbn)
2933

3034
return 0;
3135
free_resources:
36+
fbnic_free_resources(fbn);
37+
free_napi_vectors:
3238
fbnic_free_napi_vectors(fbn);
3339
return err;
3440
}
@@ -51,6 +57,7 @@ static int fbnic_stop(struct net_device *netdev)
5157

5258
fbnic_down(fbn);
5359

60+
fbnic_free_resources(fbn);
5461
fbnic_free_napi_vectors(fbn);
5562

5663
return 0;
@@ -123,6 +130,8 @@ struct net_device *fbnic_netdev_alloc(struct fbnic_dev *fbd)
123130
fbn->fbd = fbd;
124131
INIT_LIST_HEAD(&fbn->napis);
125132

133+
fbn->txq_size = FBNIC_TXQ_SIZE_DEFAULT;
134+
126135
default_queues = netif_get_num_default_rss_queues();
127136
if (default_queues > fbd->max_num_queues)
128137
default_queues = fbd->max_num_queues;

‎drivers/net/ethernet/meta/fbnic/fbnic_netdev.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@ struct fbnic_net {
1515
struct net_device *netdev;
1616
struct fbnic_dev *fbd;
1717

18+
u32 txq_size;
19+
1820
u16 num_napi;
1921

2022
u16 num_tx_queues;

‎drivers/net/ethernet/meta/fbnic/fbnic_pci.c

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -127,16 +127,33 @@ static void fbnic_service_task_stop(struct fbnic_net *fbn)
127127

128128
void fbnic_up(struct fbnic_net *fbn)
129129
{
130+
fbnic_enable(fbn);
131+
132+
/* Enable Tx/Rx processing */
133+
fbnic_napi_enable(fbn);
130134
netif_tx_start_all_queues(fbn->netdev);
131135

132136
fbnic_service_task_start(fbn);
133137
}
134138

135-
void fbnic_down(struct fbnic_net *fbn)
139+
static void fbnic_down_noidle(struct fbnic_net *fbn)
136140
{
137141
fbnic_service_task_stop(fbn);
138142

143+
/* Disable Tx/Rx Processing */
144+
fbnic_napi_disable(fbn);
139145
netif_tx_disable(fbn->netdev);
146+
147+
fbnic_disable(fbn);
148+
}
149+
150+
void fbnic_down(struct fbnic_net *fbn)
151+
{
152+
fbnic_down_noidle(fbn);
153+
154+
fbnic_wait_all_queues_idle(fbn->fbd, false);
155+
156+
fbnic_flush(fbn);
140157
}
141158

142159
static void fbnic_service_task(struct work_struct *work)

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