@@ -300,7 +300,9 @@ int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
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queue_input .mqd_addr = amdgpu_bo_gpu_offset (ring -> mqd_obj );
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queue_input .wptr_addr = ring -> wptr_gpu_addr ;
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+ amdgpu_mes_lock (& adev -> mes );
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r = adev -> mes .funcs -> map_legacy_queue (& adev -> mes , & queue_input );
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+ amdgpu_mes_unlock (& adev -> mes );
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if (r )
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DRM_ERROR ("failed to map legacy queue\n" );
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@@ -323,7 +325,9 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
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queue_input .trail_fence_addr = gpu_addr ;
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queue_input .trail_fence_data = seq ;
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+ amdgpu_mes_lock (& adev -> mes );
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r = adev -> mes .funcs -> unmap_legacy_queue (& adev -> mes , & queue_input );
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+ amdgpu_mes_unlock (& adev -> mes );
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if (r )
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DRM_ERROR ("failed to unmap legacy queue\n" );
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@@ -353,7 +357,9 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
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if (ring -> funcs -> type == AMDGPU_RING_TYPE_GFX )
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queue_input .legacy_gfx = true;
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+ amdgpu_mes_lock (& adev -> mes );
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r = adev -> mes .funcs -> reset_hw_queue (& adev -> mes , & queue_input );
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+ amdgpu_mes_unlock (& adev -> mes );
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if (r )
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DRM_ERROR ("failed to reset legacy queue\n" );
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@@ -383,7 +389,9 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
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goto error ;
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}
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+ amdgpu_mes_lock (& adev -> mes );
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r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
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+ amdgpu_mes_unlock (& adev -> mes );
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if (r )
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dev_err (adev -> dev , "failed to read reg (0x%x)\n" , reg );
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else
@@ -411,7 +419,9 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,
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goto error ;
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}
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+ amdgpu_mes_lock (& adev -> mes );
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r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
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+ amdgpu_mes_unlock (& adev -> mes );
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if (r )
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dev_err (adev -> dev , "failed to write reg (0x%x)\n" , reg );
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@@ -438,7 +448,9 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
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goto error ;
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}
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+ amdgpu_mes_lock (& adev -> mes );
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r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
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+ amdgpu_mes_unlock (& adev -> mes );
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if (r )
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dev_err (adev -> dev , "failed to reg_write_reg_wait\n" );
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@@ -463,7 +475,9 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
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goto error ;
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}
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+ amdgpu_mes_lock (& adev -> mes );
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r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
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+ amdgpu_mes_unlock (& adev -> mes );
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if (r )
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dev_err (adev -> dev , "failed to reg_write_reg_wait\n" );
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@@ -694,7 +708,9 @@ static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev,
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goto error ;
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}
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+ amdgpu_mes_lock (& adev -> mes );
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r = adev -> mes .funcs -> misc_op (& adev -> mes , & op_input );
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+ amdgpu_mes_unlock (& adev -> mes );
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if (r )
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dev_err (adev -> dev , "failed to change_config.\n" );
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