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iommu/arm-smmu-qcom: Merge table from arm-smmu-qcom-debug into match data
There is little point in having a separate match table in arm-smmu-qcom-debug.c. Merge it into the main match data table in arm-smmu-qcom.c Note, this also enables debug support for qdu1000, sm6115, sm6375 and ACPI-based sc8180x systems, since these SoCs are expected to support tlb_sync debug. Reviewed-by: Sai Prakash Ranjan <[email protected]> Tested-by: Sai Prakash Ranjan <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
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-112
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3 files changed

+45
-112
lines changed

‎drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

Lines changed: 0 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -10,16 +10,6 @@
1010
#include "arm-smmu.h"
1111
#include "arm-smmu-qcom.h"
1212

13-
enum qcom_smmu_impl_reg_offset {
14-
QCOM_SMMU_TBU_PWR_STATUS,
15-
QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
16-
QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
17-
};
18-
19-
struct qcom_smmu_config {
20-
const u32 *reg_offset;
21-
};
22-
2313
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
2414
{
2515
int ret;
@@ -59,84 +49,3 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
5949
tbu_pwr_status, sync_inv_ack, sync_inv_progress);
6050
}
6151
}
62-
63-
/* Implementation Defined Register Space 0 register offsets */
64-
static const u32 qcom_smmu_impl0_reg_offset[] = {
65-
[QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
66-
[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
67-
[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
68-
};
69-
70-
static const struct qcom_smmu_config qcm2290_smmu_cfg = {
71-
.reg_offset = qcom_smmu_impl0_reg_offset,
72-
};
73-
74-
static const struct qcom_smmu_config sc7180_smmu_cfg = {
75-
.reg_offset = qcom_smmu_impl0_reg_offset,
76-
};
77-
78-
static const struct qcom_smmu_config sc7280_smmu_cfg = {
79-
.reg_offset = qcom_smmu_impl0_reg_offset,
80-
};
81-
82-
static const struct qcom_smmu_config sc8180x_smmu_cfg = {
83-
.reg_offset = qcom_smmu_impl0_reg_offset,
84-
};
85-
86-
static const struct qcom_smmu_config sc8280xp_smmu_cfg = {
87-
.reg_offset = qcom_smmu_impl0_reg_offset,
88-
};
89-
90-
static const struct qcom_smmu_config sm6125_smmu_cfg = {
91-
.reg_offset = qcom_smmu_impl0_reg_offset,
92-
};
93-
94-
static const struct qcom_smmu_config sm6350_smmu_cfg = {
95-
.reg_offset = qcom_smmu_impl0_reg_offset,
96-
};
97-
98-
static const struct qcom_smmu_config sm8150_smmu_cfg = {
99-
.reg_offset = qcom_smmu_impl0_reg_offset,
100-
};
101-
102-
static const struct qcom_smmu_config sm8250_smmu_cfg = {
103-
.reg_offset = qcom_smmu_impl0_reg_offset,
104-
};
105-
106-
static const struct qcom_smmu_config sm8350_smmu_cfg = {
107-
.reg_offset = qcom_smmu_impl0_reg_offset,
108-
};
109-
110-
static const struct qcom_smmu_config sm8450_smmu_cfg = {
111-
.reg_offset = qcom_smmu_impl0_reg_offset,
112-
};
113-
114-
static const struct of_device_id __maybe_unused qcom_smmu_impl_debug_match[] = {
115-
{ .compatible = "qcom,msm8998-smmu-v2" },
116-
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcm2290_smmu_cfg },
117-
{ .compatible = "qcom,sc7180-smmu-500", .data = &sc7180_smmu_cfg },
118-
{ .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_cfg},
119-
{ .compatible = "qcom,sc8180x-smmu-500", .data = &sc8180x_smmu_cfg },
120-
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &sc8280xp_smmu_cfg },
121-
{ .compatible = "qcom,sdm630-smmu-v2" },
122-
{ .compatible = "qcom,sdm845-smmu-500" },
123-
{ .compatible = "qcom,sm6125-smmu-500", .data = &sm6125_smmu_cfg},
124-
{ .compatible = "qcom,sm6350-smmu-500", .data = &sm6350_smmu_cfg},
125-
{ .compatible = "qcom,sm8150-smmu-500", .data = &sm8150_smmu_cfg },
126-
{ .compatible = "qcom,sm8250-smmu-500", .data = &sm8250_smmu_cfg },
127-
{ .compatible = "qcom,sm8350-smmu-500", .data = &sm8350_smmu_cfg },
128-
{ .compatible = "qcom,sm8450-smmu-500", .data = &sm8450_smmu_cfg },
129-
{ }
130-
};
131-
132-
const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
133-
{
134-
const struct of_device_id *match;
135-
const struct device_node *np = smmu->dev->of_node;
136-
137-
match = of_match_node(qcom_smmu_impl_debug_match, np);
138-
if (!match)
139-
return NULL;
140-
141-
return match->data;
142-
}

‎drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

Lines changed: 34 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -430,11 +430,22 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
430430
return ERR_PTR(-ENOMEM);
431431

432432
qsmmu->smmu.impl = impl;
433-
qsmmu->cfg = qcom_smmu_impl_data(smmu);
433+
qsmmu->cfg = data->cfg;
434434

435435
return &qsmmu->smmu;
436436
}
437437

438+
/* Implementation Defined Register Space 0 register offsets */
439+
static const u32 qcom_smmu_impl0_reg_offset[] = {
440+
[QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
441+
[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
442+
[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
443+
};
444+
445+
static const struct qcom_smmu_config qcom_smmu_impl0_cfg = {
446+
.reg_offset = qcom_smmu_impl0_reg_offset,
447+
};
448+
438449
/*
439450
* It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
440451
* there are not enough context banks.
@@ -455,28 +466,35 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
455466
* No need for adreno impl here. On sdm845 the Adreno SMMU is handled
456467
* by the separate sdm845-smmu-v2 device.
457468
*/
469+
/* Also no debug configuration. */
470+
};
471+
472+
static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
473+
.impl = &qcom_smmu_impl,
474+
.adreno_impl = &qcom_adreno_smmu_impl,
475+
.cfg = &qcom_smmu_impl0_cfg,
458476
};
459477

460478
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
461479
{ .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
462480
{ .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_data },
463-
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_data },
464-
{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_data },
465-
{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_data },
466-
{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_data },
467-
{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_data },
468-
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_data },
481+
{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
482+
{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
483+
{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
484+
{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
485+
{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
486+
{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
469487
{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_data },
470488
{ .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_data },
471489
{ .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
472-
{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_data },
473-
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_data },
474-
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_data },
475-
{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_data },
476-
{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_data },
477-
{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_data },
478-
{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_data },
479-
{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_data },
490+
{ .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
491+
{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
492+
{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
493+
{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
494+
{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
495+
{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
496+
{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
497+
{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
480498
{ }
481499
};
482500

@@ -497,7 +515,7 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
497515
if (np == NULL) {
498516
/* Match platform for ACPI boot */
499517
if (acpi_match_platform_list(qcom_acpi_platlist) >= 0)
500-
return qcom_smmu_create(smmu, &qcom_smmu_data);
518+
return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data);
501519
}
502520
#endif
503521

‎drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,20 +14,26 @@ struct qcom_smmu {
1414
u32 stall_enabled;
1515
};
1616

17+
enum qcom_smmu_impl_reg_offset {
18+
QCOM_SMMU_TBU_PWR_STATUS,
19+
QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
20+
QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
21+
};
22+
23+
struct qcom_smmu_config {
24+
const u32 *reg_offset;
25+
};
26+
1727
struct qcom_smmu_match_data {
28+
const struct qcom_smmu_config *cfg;
1829
const struct arm_smmu_impl *impl;
1930
const struct arm_smmu_impl *adreno_impl;
2031
};
2132

2233
#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
2334
void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
24-
const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu);
2535
#else
2636
static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }
27-
static inline const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
28-
{
29-
return NULL;
30-
}
3137
#endif
3238

3339
#endif /* _ARM_SMMU_QCOM_H */

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