@@ -189,6 +189,59 @@ TEST_F(user, perf_write) {
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ASSERT_EQ (0 , self -> check );
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}
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+ TEST_F (user , perf_empty_events ) {
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+ struct perf_event_attr pe = {0 };
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+ struct user_reg reg = {0 };
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+ struct perf_event_mmap_page * perf_page ;
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+ int page_size = sysconf (_SC_PAGESIZE );
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+ int id , fd ;
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+ __u32 * val ;
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+
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+ reg .size = sizeof (reg );
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+ reg .name_args = (__u64 )"__test_event" ;
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+ reg .enable_bit = 31 ;
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+ reg .enable_addr = (__u64 )& self -> check ;
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+ reg .enable_size = sizeof (self -> check );
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+
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+ /* Register should work */
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+ ASSERT_EQ (0 , ioctl (self -> data_fd , DIAG_IOCSREG , & reg ));
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+ ASSERT_EQ (0 , reg .write_index );
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+ ASSERT_EQ (0 , self -> check );
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+
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+ /* Id should be there */
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+ id = get_id ();
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+ ASSERT_NE (-1 , id );
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+
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+ pe .type = PERF_TYPE_TRACEPOINT ;
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+ pe .size = sizeof (pe );
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+ pe .config = id ;
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+ pe .sample_type = PERF_SAMPLE_RAW ;
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+ pe .sample_period = 1 ;
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+ pe .wakeup_events = 1 ;
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+
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+ /* Tracepoint attach should work */
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+ fd = perf_event_open (& pe , 0 , -1 , -1 , 0 );
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+ ASSERT_NE (-1 , fd );
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+
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+ perf_page = mmap (NULL , page_size * 2 , PROT_READ , MAP_SHARED , fd , 0 );
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+ ASSERT_NE (MAP_FAILED , perf_page );
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+
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+ /* Status should be updated */
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+ ASSERT_EQ (1 << reg .enable_bit , self -> check );
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+
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+ /* Ensure write shows up at correct offset */
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+ ASSERT_NE (-1 , write (self -> data_fd , & reg .write_index ,
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+ sizeof (reg .write_index )));
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+ val = (void * )(((char * )perf_page ) + perf_page -> data_offset );
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+ ASSERT_EQ (PERF_RECORD_SAMPLE , * val );
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+
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+ munmap (perf_page , page_size * 2 );
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+ close (fd );
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+
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+ /* Status should be updated */
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+ ASSERT_EQ (0 , self -> check );
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+ }
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+
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int main (int argc , char * * argv )
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{
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return test_harness_run (argc , argv );
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