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clk: tegra30: Use custom CCLK implementation
We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation. Acked-by: Peter De Schrijver <[email protected]> Tested-by: Peter Geis <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Tested-by: Jasper Korten <[email protected]> Tested-by: David Heidelberg <[email protected]> Tested-by: Nicolas Chauvet <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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drivers/clk/tegra/clk-tegra30.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
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.freq_table = pll_x_freq_table,
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.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
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TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
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.pre_rate_change = tegra_cclk_pre_pllx_rate_change,
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.post_rate_change = tegra_cclk_post_pllx_rate_change,
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};
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static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
@@ -926,11 +928,11 @@ static void __init tegra30_super_clk_init(void)
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clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
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/* CCLKG */
929-
clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
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clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
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ARRAY_SIZE(cclk_g_parents),
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CLK_SET_RATE_PARENT,
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clk_base + CCLKG_BURST_POLICY,
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0, 4, 0, 0, NULL);
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0, NULL);
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clks[TEGRA30_CLK_CCLK_G] = clk;
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/*

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