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* Copyright (c) 2015 The Linux Foundation. All rights reserved.
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*/
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- #define EDL_PATCH_CMD_OPCODE ( 0xFC00)
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- #define EDL_NVM_ACCESS_OPCODE ( 0xFC0B)
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- #define EDL_WRITE_BD_ADDR_OPCODE ( 0xFC14)
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- #define EDL_PATCH_CMD_LEN (1)
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- #define EDL_PATCH_VER_REQ_CMD ( 0x19)
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- #define EDL_PATCH_TLV_REQ_CMD ( 0x1E)
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- #define EDL_GET_BUILD_INFO_CMD ( 0x20)
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- #define EDL_GET_BID_REQ_CMD ( 0x23)
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- #define EDL_NVM_ACCESS_SET_REQ_CMD ( 0x01)
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- #define EDL_PATCH_CONFIG_CMD ( 0x28)
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- #define MAX_SIZE_PER_TLV_SEGMENT ( 243)
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- #define QCA_PRE_SHUTDOWN_CMD ( 0xFC08)
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- #define QCA_DISABLE_LOGGING ( 0xFC17)
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-
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- #define EDL_CMD_REQ_RES_EVT ( 0x00)
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- #define EDL_PATCH_VER_RES_EVT ( 0x19)
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- #define EDL_APP_VER_RES_EVT ( 0x02)
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- #define EDL_TVL_DNLD_RES_EVT ( 0x04)
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- #define EDL_CMD_EXE_STATUS_EVT ( 0x00)
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- #define EDL_SET_BAUDRATE_RSP_EVT ( 0x92)
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- #define EDL_NVM_ACCESS_CODE_EVT ( 0x0B)
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- #define EDL_PATCH_CONFIG_RES_EVT ( 0x00)
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- #define QCA_DISABLE_LOGGING_SUB_OP ( 0x14)
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+ #define EDL_PATCH_CMD_OPCODE 0xFC00
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+ #define EDL_NVM_ACCESS_OPCODE 0xFC0B
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+ #define EDL_WRITE_BD_ADDR_OPCODE 0xFC14
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+ #define EDL_PATCH_CMD_LEN 1
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+ #define EDL_PATCH_VER_REQ_CMD 0x19
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+ #define EDL_PATCH_TLV_REQ_CMD 0x1E
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+ #define EDL_GET_BUILD_INFO_CMD 0x20
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+ #define EDL_GET_BID_REQ_CMD 0x23
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+ #define EDL_NVM_ACCESS_SET_REQ_CMD 0x01
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+ #define EDL_PATCH_CONFIG_CMD 0x28
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+ #define MAX_SIZE_PER_TLV_SEGMENT 243
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+ #define QCA_PRE_SHUTDOWN_CMD 0xFC08
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+ #define QCA_DISABLE_LOGGING 0xFC17
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+
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+ #define EDL_CMD_REQ_RES_EVT 0x00
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+ #define EDL_PATCH_VER_RES_EVT 0x19
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+ #define EDL_APP_VER_RES_EVT 0x02
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+ #define EDL_TVL_DNLD_RES_EVT 0x04
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+ #define EDL_CMD_EXE_STATUS_EVT 0x00
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+ #define EDL_SET_BAUDRATE_RSP_EVT 0x92
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+ #define EDL_NVM_ACCESS_CODE_EVT 0x0B
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+ #define EDL_PATCH_CONFIG_RES_EVT 0x00
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+ #define QCA_DISABLE_LOGGING_SUB_OP 0x14
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#define EDL_TAG_ID_BD_ADDR 2
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- #define EDL_TAG_ID_HCI (17)
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- #define EDL_TAG_ID_DEEP_SLEEP (27)
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+ #define EDL_TAG_ID_HCI 17
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+ #define EDL_TAG_ID_DEEP_SLEEP 27
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#define QCA_WCN3990_POWERON_PULSE 0xFC
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#define QCA_WCN3990_POWEROFF_PULSE 0xC0
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#define QCA_HCI_CC_OPCODE 0xFC00
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#define QCA_HCI_CC_SUCCESS 0x00
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- #define QCA_WCN3991_SOC_ID ( 0x40014320)
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+ #define QCA_WCN3991_SOC_ID 0x40014320
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/* QCA chipset version can be decided by patch and SoC
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* version, combination with upper 2 bytes from SoC
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#define get_soc_ver (soc_id , rom_ver ) \
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((le32_to_cpu(soc_id) << 16) | (le16_to_cpu(rom_ver)))
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- #define QCA_HSP_GF_SOC_ID 0x1200
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- #define QCA_HSP_GF_SOC_MASK 0x0000ff00
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+ #define QCA_HSP_GF_SOC_ID 0x1200
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+ #define QCA_HSP_GF_SOC_MASK 0x0000ff00
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enum qca_baudrate {
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- QCA_BAUDRATE_115200 = 0 ,
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+ QCA_BAUDRATE_115200 = 0 ,
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QCA_BAUDRATE_57600 ,
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QCA_BAUDRATE_38400 ,
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QCA_BAUDRATE_19200 ,
@@ -71,7 +71,7 @@ enum qca_baudrate {
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QCA_BAUDRATE_1600000 ,
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QCA_BAUDRATE_3200000 ,
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QCA_BAUDRATE_3500000 ,
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- QCA_BAUDRATE_AUTO = 0xFE ,
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+ QCA_BAUDRATE_AUTO = 0xFE ,
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QCA_BAUDRATE_RESERVED
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};
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