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Merge tag 'riscv-for-linus-5.8-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt: - The remainder of the code necessary to support the Kendryte K210: * Support for building device trees into the kernel, as the K210 doesn't have a bootloader that provides one * A K210 device tree and the associated defconfig update * Support for skipping PMP initialization on systems that trap on PMP accesses rather than treating them as WARL - Support for KGDB - Improvements to text patching - Some cleanups to the SiFive L2 cache driver * tag 'riscv-for-linus-5.8-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: soc: sifive: l2 cache: Mark l2_get_priv_group as static soc: sifive: l2 cache: Eliminate an unsigned zero compare warning riscv: Add support to determine no. of L2 cache way enabled riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure riscv: Use text_mutex instead of patch_lock riscv: Use NOKPROBE_SYMBOL() instead of __krpobes annotation riscv: Remove the 'riscv_' prefix of function name riscv: Add SW single-step support for KDB riscv: Use the XML target descriptions to report 3 system registers riscv: Add KGDB support kgdb: Add kgdb_has_hit_break function RISC-V: Skip setting up PMPs on traps riscv: K210: Update defconfig riscv: K210: Add a built-in device tree riscv: Allow device trees to be built into the kernel
2 parents 571d54e + 09c0533 commit 435faf5

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‎arch/riscv/Kbuild

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@@ -1,3 +1,4 @@
11
# SPDX-License-Identifier: GPL-2.0-only
22

33
obj-y += kernel/ mm/ net/
4+
obj-$(CONFIG_BUILTIN_DTB) += boot/dts/

‎arch/riscv/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -68,6 +68,8 @@ config RISCV
6868
select ARCH_HAS_GCOV_PROFILE_ALL
6969
select HAVE_COPY_THREAD_TLS
7070
select HAVE_ARCH_KASAN if MMU && 64BIT
71+
select HAVE_ARCH_KGDB
72+
select HAVE_ARCH_KGDB_QXFER_PKT
7173

7274
config ARCH_MMAP_RND_BITS_MIN
7375
default 18 if 64BIT
@@ -381,6 +383,11 @@ endchoice
381383

382384
endmenu
383385

386+
config BUILTIN_DTB
387+
def_bool n
388+
depends on RISCV_M_MODE
389+
depends on OF
390+
384391
menu "Power management options"
385392

386393
source "kernel/power/Kconfig"

‎arch/riscv/Kconfig.socs

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Original file line numberDiff line numberDiff line change
@@ -24,11 +24,26 @@ config SOC_VIRT
2424
config SOC_KENDRYTE
2525
bool "Kendryte K210 SoC"
2626
depends on !MMU
27-
select BUILTIN_DTB
2827
select SERIAL_SIFIVE if TTY
2928
select SERIAL_SIFIVE_CONSOLE if TTY
3029
select SIFIVE_PLIC
3130
help
3231
This enables support for Kendryte K210 SoC platform hardware.
3332

33+
config SOC_KENDRYTE_K210_DTB
34+
def_bool y
35+
depends on SOC_KENDRYTE_K210_DTB_BUILTIN
36+
37+
config SOC_KENDRYTE_K210_DTB_BUILTIN
38+
bool "Builtin device tree for the Kendryte K210"
39+
depends on SOC_KENDRYTE
40+
default y
41+
select OF
42+
select BUILTIN_DTB
43+
select SOC_KENDRYTE_K210_DTB
44+
help
45+
Builds a device tree for the Kendryte K210 into the Linux image.
46+
This option should be selected if no bootloader is being used.
47+
If unsure, say Y.
48+
3449
endmenu

‎arch/riscv/boot/dts/Makefile

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Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
11
# SPDX-License-Identifier: GPL-2.0
22
subdir-y += sifive
33
subdir-y += kendryte
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obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

‎arch/riscv/boot/dts/kendryte/Makefile

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Original file line numberDiff line numberDiff line change
@@ -1,2 +1,4 @@
11
# SPDX-License-Identifier: GPL-2.0
2-
dtb-$(CONFIG_SOC_KENDRYTE) += k210.dtb
2+
dtb-$(CONFIG_SOC_KENDRYTE_K210_DTB) += k210.dtb
3+
4+
obj-$(CONFIG_SOC_KENDRYTE_K210_DTB_BUILTIN) += $(addsuffix .o, $(dtb-y))

‎arch/riscv/configs/nommu_k210_defconfig

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@@ -2,14 +2,12 @@
22
CONFIG_LOG_BUF_SHIFT=15
33
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12
44
CONFIG_BLK_DEV_INITRD=y
5-
CONFIG_INITRAMFS_SOURCE=""
65
CONFIG_INITRAMFS_FORCE=y
76
# CONFIG_RD_BZIP2 is not set
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# CONFIG_RD_LZMA is not set
98
# CONFIG_RD_XZ is not set
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# CONFIG_RD_LZO is not set
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# CONFIG_RD_LZ4 is not set
12-
# CONFIG_BOOT_CONFIG is not set
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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# CONFIG_SYSFS_SYSCALL is not set
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# CONFIG_FHANDLE is not set
@@ -35,8 +33,6 @@ CONFIG_SMP=y
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CONFIG_NR_CPUS=2
3634
CONFIG_CMDLINE="earlycon console=ttySIF0"
3735
CONFIG_CMDLINE_FORCE=y
38-
CONFIG_USE_BUILTIN_DTB=y
39-
CONFIG_BUILTIN_DTB_SOURCE="kendryte/k210"
4036
# CONFIG_BLOCK is not set
4137
CONFIG_BINFMT_FLAT=y
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# CONFIG_COREDUMP is not set
@@ -49,8 +45,8 @@ CONFIG_DEVTMPFS_MOUNT=y
4945
# CONFIG_SERIO is not set
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# CONFIG_LEGACY_PTYS is not set
5147
# CONFIG_LDISC_AUTOLOAD is not set
52-
# CONFIG_DEVMEM is not set
5348
# CONFIG_HW_RANDOM is not set
49+
# CONFIG_DEVMEM is not set
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# CONFIG_HWMON is not set
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# CONFIG_VGA_CONSOLE is not set
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# CONFIG_HID is not set
@@ -62,6 +58,7 @@ CONFIG_DEVTMPFS_MOUNT=y
6258
CONFIG_LSM="[]"
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CONFIG_PRINTK_TIME=y
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# CONFIG_DEBUG_MISC is not set
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CONFIG_PANIC_ON_OOPS=y
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# CONFIG_SCHED_DEBUG is not set
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# CONFIG_RCU_TRACE is not set
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# CONFIG_FTRACE is not set

‎arch/riscv/include/asm/cacheinfo.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_CACHEINFO_H
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#define _ASM_RISCV_CACHEINFO_H
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#include <linux/cacheinfo.h>
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struct riscv_cacheinfo_ops {
9+
const struct attribute_group * (*get_priv_group)(struct cacheinfo
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*this_leaf);
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};
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void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops);
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#endif /* _ASM_RISCV_CACHEINFO_H */

‎arch/riscv/include/asm/gdb_xml.h

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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_GDB_XML_H_
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#define __ASM_GDB_XML_H_
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#define kgdb_arch_gdb_stub_feature riscv_gdb_stub_feature
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static const char riscv_gdb_stub_feature[64] =
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"PacketSize=800;qXfer:features:read+;";
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static const char gdb_xfer_read_target[31] = "qXfer:features:read:target.xml:";
11+
12+
#ifdef CONFIG_64BIT
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static const char gdb_xfer_read_cpuxml[39] =
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"qXfer:features:read:riscv-64bit-cpu.xml";
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static const char riscv_gdb_stub_target_desc[256] =
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"l<?xml version=\"1.0\"?>"
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"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
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"<target>"
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"<xi:include href=\"riscv-64bit-cpu.xml\"/>"
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"</target>";
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static const char riscv_gdb_stub_cpuxml[2048] =
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"l<?xml version=\"1.0\"?>"
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"<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"
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"<feature name=\"org.gnu.gdb.riscv.cpu\">"
27+
"<reg name=\""DBG_REG_ZERO"\" bitsize=\"64\" type=\"int\" regnum=\"0\"/>"
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"<reg name=\""DBG_REG_RA"\" bitsize=\"64\" type=\"code_ptr\"/>"
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"<reg name=\""DBG_REG_SP"\" bitsize=\"64\" type=\"data_ptr\"/>"
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"<reg name=\""DBG_REG_GP"\" bitsize=\"64\" type=\"data_ptr\"/>"
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"<reg name=\""DBG_REG_TP"\" bitsize=\"64\" type=\"data_ptr\"/>"
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"<reg name=\""DBG_REG_T0"\" bitsize=\"64\" type=\"int\"/>"
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"<reg name=\""DBG_REG_T1"\" bitsize=\"64\" type=\"int\"/>"
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"<reg name=\""DBG_REG_T2"\" bitsize=\"64\" type=\"int\"/>"
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"<reg name=\""DBG_REG_FP"\" bitsize=\"64\" type=\"data_ptr\"/>"
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"<reg name=\""DBG_REG_S1"\" bitsize=\"64\" type=\"int\"/>"
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"<reg name=\""DBG_REG_A0"\" bitsize=\"64\" type=\"int\"/>"
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"<reg name=\""DBG_REG_A1"\" bitsize=\"64\" type=\"int\"/>"
39+
"<reg name=\""DBG_REG_A2"\" bitsize=\"64\" type=\"int\"/>"
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"<reg name=\""DBG_REG_A3"\" bitsize=\"64\" type=\"int\"/>"
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"<reg name=\""DBG_REG_A4"\" bitsize=\"64\" type=\"int\"/>"
42+
"<reg name=\""DBG_REG_A5"\" bitsize=\"64\" type=\"int\"/>"
43+
"<reg name=\""DBG_REG_A6"\" bitsize=\"64\" type=\"int\"/>"
44+
"<reg name=\""DBG_REG_A7"\" bitsize=\"64\" type=\"int\"/>"
45+
"<reg name=\""DBG_REG_S2"\" bitsize=\"64\" type=\"int\"/>"
46+
"<reg name=\""DBG_REG_S3"\" bitsize=\"64\" type=\"int\"/>"
47+
"<reg name=\""DBG_REG_S4"\" bitsize=\"64\" type=\"int\"/>"
48+
"<reg name=\""DBG_REG_S5"\" bitsize=\"64\" type=\"int\"/>"
49+
"<reg name=\""DBG_REG_S6"\" bitsize=\"64\" type=\"int\"/>"
50+
"<reg name=\""DBG_REG_S7"\" bitsize=\"64\" type=\"int\"/>"
51+
"<reg name=\""DBG_REG_S8"\" bitsize=\"64\" type=\"int\"/>"
52+
"<reg name=\""DBG_REG_S9"\" bitsize=\"64\" type=\"int\"/>"
53+
"<reg name=\""DBG_REG_S10"\" bitsize=\"64\" type=\"int\"/>"
54+
"<reg name=\""DBG_REG_S11"\" bitsize=\"64\" type=\"int\"/>"
55+
"<reg name=\""DBG_REG_T3"\" bitsize=\"64\" type=\"int\"/>"
56+
"<reg name=\""DBG_REG_T4"\" bitsize=\"64\" type=\"int\"/>"
57+
"<reg name=\""DBG_REG_T5"\" bitsize=\"64\" type=\"int\"/>"
58+
"<reg name=\""DBG_REG_T6"\" bitsize=\"64\" type=\"int\"/>"
59+
"<reg name=\""DBG_REG_EPC"\" bitsize=\"64\" type=\"code_ptr\"/>"
60+
"<reg name=\""DBG_REG_STATUS"\" bitsize=\"64\" type=\"int\"/>"
61+
"<reg name=\""DBG_REG_BADADDR"\" bitsize=\"64\" type=\"int\"/>"
62+
"<reg name=\""DBG_REG_CAUSE"\" bitsize=\"64\" type=\"int\"/>"
63+
"</feature>";
64+
#else
65+
static const char gdb_xfer_read_cpuxml[39] =
66+
"qXfer:features:read:riscv-32bit-cpu.xml";
67+
68+
static const char riscv_gdb_stub_target_desc[256] =
69+
"l<?xml version=\"1.0\"?>"
70+
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
71+
"<target>"
72+
"<xi:include href=\"riscv-32bit-cpu.xml\"/>"
73+
"</target>";
74+
75+
static const char riscv_gdb_stub_cpuxml[2048] =
76+
"l<?xml version=\"1.0\"?>"
77+
"<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"
78+
"<feature name=\"org.gnu.gdb.riscv.cpu\">"
79+
"<reg name=\""DBG_REG_ZERO"\" bitsize=\"32\" type=\"int\" regnum=\"0\"/>"
80+
"<reg name=\""DBG_REG_RA"\" bitsize=\"32\" type=\"code_ptr\"/>"
81+
"<reg name=\""DBG_REG_SP"\" bitsize=\"32\" type=\"data_ptr\"/>"
82+
"<reg name=\""DBG_REG_GP"\" bitsize=\"32\" type=\"data_ptr\"/>"
83+
"<reg name=\""DBG_REG_TP"\" bitsize=\"32\" type=\"data_ptr\"/>"
84+
"<reg name=\""DBG_REG_T0"\" bitsize=\"32\" type=\"int\"/>"
85+
"<reg name=\""DBG_REG_T1"\" bitsize=\"32\" type=\"int\"/>"
86+
"<reg name=\""DBG_REG_T2"\" bitsize=\"32\" type=\"int\"/>"
87+
"<reg name=\""DBG_REG_FP"\" bitsize=\"32\" type=\"data_ptr\"/>"
88+
"<reg name=\""DBG_REG_S1"\" bitsize=\"32\" type=\"int\"/>"
89+
"<reg name=\""DBG_REG_A0"\" bitsize=\"32\" type=\"int\"/>"
90+
"<reg name=\""DBG_REG_A1"\" bitsize=\"32\" type=\"int\"/>"
91+
"<reg name=\""DBG_REG_A2"\" bitsize=\"32\" type=\"int\"/>"
92+
"<reg name=\""DBG_REG_A3"\" bitsize=\"32\" type=\"int\"/>"
93+
"<reg name=\""DBG_REG_A4"\" bitsize=\"32\" type=\"int\"/>"
94+
"<reg name=\""DBG_REG_A5"\" bitsize=\"32\" type=\"int\"/>"
95+
"<reg name=\""DBG_REG_A6"\" bitsize=\"32\" type=\"int\"/>"
96+
"<reg name=\""DBG_REG_A7"\" bitsize=\"32\" type=\"int\"/>"
97+
"<reg name=\""DBG_REG_S2"\" bitsize=\"32\" type=\"int\"/>"
98+
"<reg name=\""DBG_REG_S3"\" bitsize=\"32\" type=\"int\"/>"
99+
"<reg name=\""DBG_REG_S4"\" bitsize=\"32\" type=\"int\"/>"
100+
"<reg name=\""DBG_REG_S5"\" bitsize=\"32\" type=\"int\"/>"
101+
"<reg name=\""DBG_REG_S6"\" bitsize=\"32\" type=\"int\"/>"
102+
"<reg name=\""DBG_REG_S7"\" bitsize=\"32\" type=\"int\"/>"
103+
"<reg name=\""DBG_REG_S8"\" bitsize=\"32\" type=\"int\"/>"
104+
"<reg name=\""DBG_REG_S9"\" bitsize=\"32\" type=\"int\"/>"
105+
"<reg name=\""DBG_REG_S10"\" bitsize=\"32\" type=\"int\"/>"
106+
"<reg name=\""DBG_REG_S11"\" bitsize=\"32\" type=\"int\"/>"
107+
"<reg name=\""DBG_REG_T3"\" bitsize=\"32\" type=\"int\"/>"
108+
"<reg name=\""DBG_REG_T4"\" bitsize=\"32\" type=\"int\"/>"
109+
"<reg name=\""DBG_REG_T5"\" bitsize=\"32\" type=\"int\"/>"
110+
"<reg name=\""DBG_REG_T6"\" bitsize=\"32\" type=\"int\"/>"
111+
"<reg name=\""DBG_REG_EPC"\" bitsize=\"32\" type=\"code_ptr\"/>"
112+
"<reg name=\""DBG_REG_STATUS"\" bitsize=\"32\" type=\"int\"/>"
113+
"<reg name=\""DBG_REG_BADADDR"\" bitsize=\"32\" type=\"int\"/>"
114+
"<reg name=\""DBG_REG_CAUSE"\" bitsize=\"32\" type=\"int\"/>"
115+
"</feature>";
116+
#endif
117+
#endif

‎arch/riscv/include/asm/kdebug.h

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@@ -0,0 +1,12 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
3+
#ifndef _ASM_ARC_KDEBUG_H
4+
#define _ASM_ARC_KDEBUG_H
5+
6+
enum die_val {
7+
DIE_UNUSED,
8+
DIE_TRAP,
9+
DIE_OOPS
10+
};
11+
12+
#endif

‎arch/riscv/include/asm/kgdb.h

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,112 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
3+
#ifndef __ASM_KGDB_H_
4+
#define __ASM_KGDB_H_
5+
6+
#ifdef __KERNEL__
7+
8+
#define GDB_SIZEOF_REG sizeof(unsigned long)
9+
10+
#define DBG_MAX_REG_NUM (36)
11+
#define NUMREGBYTES ((DBG_MAX_REG_NUM) * GDB_SIZEOF_REG)
12+
#define CACHE_FLUSH_IS_SAFE 1
13+
#define BUFMAX 2048
14+
#ifdef CONFIG_RISCV_ISA_C
15+
#define BREAK_INSTR_SIZE 2
16+
#else
17+
#define BREAK_INSTR_SIZE 4
18+
#endif
19+
20+
#ifndef __ASSEMBLY__
21+
22+
extern int kgdb_has_hit_break(unsigned long addr);
23+
extern unsigned long kgdb_compiled_break;
24+
25+
static inline void arch_kgdb_breakpoint(void)
26+
{
27+
asm(".global kgdb_compiled_break\n"
28+
".option norvc\n"
29+
"kgdb_compiled_break: ebreak\n"
30+
".option rvc\n");
31+
}
32+
33+
#endif /* !__ASSEMBLY__ */
34+
35+
#define DBG_REG_ZERO "zero"
36+
#define DBG_REG_RA "ra"
37+
#define DBG_REG_SP "sp"
38+
#define DBG_REG_GP "gp"
39+
#define DBG_REG_TP "tp"
40+
#define DBG_REG_T0 "t0"
41+
#define DBG_REG_T1 "t1"
42+
#define DBG_REG_T2 "t2"
43+
#define DBG_REG_FP "fp"
44+
#define DBG_REG_S1 "s1"
45+
#define DBG_REG_A0 "a0"
46+
#define DBG_REG_A1 "a1"
47+
#define DBG_REG_A2 "a2"
48+
#define DBG_REG_A3 "a3"
49+
#define DBG_REG_A4 "a4"
50+
#define DBG_REG_A5 "a5"
51+
#define DBG_REG_A6 "a6"
52+
#define DBG_REG_A7 "a7"
53+
#define DBG_REG_S2 "s2"
54+
#define DBG_REG_S3 "s3"
55+
#define DBG_REG_S4 "s4"
56+
#define DBG_REG_S5 "s5"
57+
#define DBG_REG_S6 "s6"
58+
#define DBG_REG_S7 "s7"
59+
#define DBG_REG_S8 "s8"
60+
#define DBG_REG_S9 "s9"
61+
#define DBG_REG_S10 "s10"
62+
#define DBG_REG_S11 "s11"
63+
#define DBG_REG_T3 "t3"
64+
#define DBG_REG_T4 "t4"
65+
#define DBG_REG_T5 "t5"
66+
#define DBG_REG_T6 "t6"
67+
#define DBG_REG_EPC "pc"
68+
#define DBG_REG_STATUS "sstatus"
69+
#define DBG_REG_BADADDR "stval"
70+
#define DBG_REG_CAUSE "scause"
71+
72+
#define DBG_REG_ZERO_OFF 0
73+
#define DBG_REG_RA_OFF 1
74+
#define DBG_REG_SP_OFF 2
75+
#define DBG_REG_GP_OFF 3
76+
#define DBG_REG_TP_OFF 4
77+
#define DBG_REG_T0_OFF 5
78+
#define DBG_REG_T1_OFF 6
79+
#define DBG_REG_T2_OFF 7
80+
#define DBG_REG_FP_OFF 8
81+
#define DBG_REG_S1_OFF 9
82+
#define DBG_REG_A0_OFF 10
83+
#define DBG_REG_A1_OFF 11
84+
#define DBG_REG_A2_OFF 12
85+
#define DBG_REG_A3_OFF 13
86+
#define DBG_REG_A4_OFF 14
87+
#define DBG_REG_A5_OFF 15
88+
#define DBG_REG_A6_OFF 16
89+
#define DBG_REG_A7_OFF 17
90+
#define DBG_REG_S2_OFF 18
91+
#define DBG_REG_S3_OFF 19
92+
#define DBG_REG_S4_OFF 20
93+
#define DBG_REG_S5_OFF 21
94+
#define DBG_REG_S6_OFF 22
95+
#define DBG_REG_S7_OFF 23
96+
#define DBG_REG_S8_OFF 24
97+
#define DBG_REG_S9_OFF 25
98+
#define DBG_REG_S10_OFF 26
99+
#define DBG_REG_S11_OFF 27
100+
#define DBG_REG_T3_OFF 28
101+
#define DBG_REG_T4_OFF 29
102+
#define DBG_REG_T5_OFF 30
103+
#define DBG_REG_T6_OFF 31
104+
#define DBG_REG_EPC_OFF 32
105+
#define DBG_REG_STATUS_OFF 33
106+
#define DBG_REG_BADADDR_OFF 34
107+
#define DBG_REG_CAUSE_OFF 35
108+
109+
#include <asm/gdb_xml.h>
110+
111+
#endif
112+
#endif

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