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torvaldstorvalds
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Merge tag 'drm-fixes-2020-08-21' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Regular fixes pull for rc2. Usual rc2 doesn't seem too busy, mainly i915 and amdgpu. I'd expect the usual uptick for rc3. amdgpu: - Fix allocation size - SR-IOV fixes - Vega20 SMU feature state caching fix - Fix custom pptable handling - Arcturus golden settings update - Several display fixes - Fixes for Navy Flounder - Misc display fixes - RAS fix amdkfd: - SDMA fix for renoir i915: - Fix device parameter usage for selftest mock i915 device - Fix LPSP capability debugfs NULL dereference - Fix buddy register pagemask table - Fix intel_atomic_check() non-negative return value - Fix selftests passing a random 0 into ilog2() - Fix TGL power well enable/disable ordering - Switch to PMU module refcounting - GVT fixes virtio: - Add missing dma_fence_put() in virtio_gpu_execbuffer_ioctl() - Fix memory leak in virtio_gpu_cleanup_object()" * tag 'drm-fixes-2020-08-21' of git://anongit.freedesktop.org/drm/drm: (34 commits) Revert "drm/amdgpu: disable gfxoff for navy_flounder" drm/i915/tgl: Make sure TC-cold is blocked before enabling TC AUX power wells drm/i915/selftests: Avoid passing a random 0 into ilog2 drm/i915: Fix wrong return value in intel_atomic_check() drm/i915: Update bw_buddy pagemask table drm/i915/display: Check for an LPSP encoder before dereferencing drm/i915: Copy default modparams to mock i915_device drm/i915: Provide the perf pmu.module drm/amd/display: fix pow() crashing when given base 0 drm/amd/display: Reset scrambling on Test Pattern drm/amd/display: fix dcn3 wide timing dsc validation drm/amd/display: Fix DFPstate hang due to view port changed drm/amd/display: Assign correct left shift drm/amd/display: Call DMUB for eDP power control drm/amdkfd: fix the wrong sdma instance query for renoir drm/amdgpu: parse ta firmware for navy_flounder drm/amdgpu: fix NULL pointer access issue when unloading driver drm/amdgpu: fix uninit-value in arcturus_log_thermal_throttling_event() drm/amdgpu: disable gfxoff for navy_flounder drm/amdgpu/display: use GFP_ATOMIC in dcn20_validate_bandwidth_internal ...
2 parents da2968f + 0790e63 commit 43d387a

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41 files changed

+317
-94
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

Lines changed: 22 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -195,19 +195,32 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
195195
unsigned int engine_id,
196196
unsigned int queue_id)
197197
{
198-
uint32_t sdma_engine_reg_base[2] = {
199-
SOC15_REG_OFFSET(SDMA0, 0,
200-
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
201-
SOC15_REG_OFFSET(SDMA1, 0,
202-
mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL
203-
};
204-
uint32_t retval = sdma_engine_reg_base[engine_id]
198+
uint32_t sdma_engine_reg_base = 0;
199+
uint32_t sdma_rlc_reg_offset;
200+
201+
switch (engine_id) {
202+
default:
203+
dev_warn(adev->dev,
204+
"Invalid sdma engine id (%d), using engine id 0\n",
205+
engine_id);
206+
fallthrough;
207+
case 0:
208+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
209+
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
210+
break;
211+
case 1:
212+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
213+
mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
214+
break;
215+
}
216+
217+
sdma_rlc_reg_offset = sdma_engine_reg_base
205218
+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
206219

207220
pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
208-
queue_id, retval);
221+
queue_id, sdma_rlc_reg_offset);
209222

210-
return retval;
223+
return sdma_rlc_reg_offset;
211224
}
212225

213226
static inline struct v9_mqd *get_mqd(void *mqd)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1243,7 +1243,6 @@ void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
12431243
if (!obj || !obj->ent)
12441244
return;
12451245

1246-
debugfs_remove(obj->ent);
12471246
obj->ent = NULL;
12481247
put_obj(obj);
12491248
}
@@ -1257,7 +1256,6 @@ static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
12571256
amdgpu_ras_debugfs_remove(adev, &obj->head);
12581257
}
12591258

1260-
debugfs_remove_recursive(con->dir);
12611259
con->dir = NULL;
12621260
}
12631261
/* debugfs end */

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -462,7 +462,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
462462
unsigned int pages;
463463
int i, r;
464464

465-
*sgt = kmalloc(sizeof(*sg), GFP_KERNEL);
465+
*sgt = kmalloc(sizeof(**sgt), GFP_KERNEL);
466466
if (!*sgt)
467467
return -ENOMEM;
468468

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -691,6 +691,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
691691
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
692692
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
693693
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
694+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)
694695
};
695696

696697
static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {

‎drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,12 @@ static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
135135
{
136136
uint32_t tmp;
137137

138+
/* These registers are not accessible to VF-SRIOV.
139+
* The PF will program them instead.
140+
*/
141+
if (amdgpu_sriov_vf(adev))
142+
return;
143+
138144
/* Setup L2 cache */
139145
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
140146
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -190,6 +196,12 @@ static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
190196

191197
static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
192198
{
199+
/* These registers are not accessible to VF-SRIOV.
200+
* The PF will program them instead.
201+
*/
202+
if (amdgpu_sriov_vf(adev))
203+
return;
204+
193205
WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
194206
0xFFFFFFFF);
195207
WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
@@ -326,6 +338,13 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
326338
bool value)
327339
{
328340
u32 tmp;
341+
342+
/* These registers are not accessible to VF-SRIOV.
343+
* The PF will program them instead.
344+
*/
345+
if (amdgpu_sriov_vf(adev))
346+
return;
347+
329348
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
330349
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
331350
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

‎drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,12 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
134134
{
135135
uint32_t tmp;
136136

137+
/* These registers are not accessible to VF-SRIOV.
138+
* The PF will program them instead.
139+
*/
140+
if (amdgpu_sriov_vf(adev))
141+
return;
142+
137143
/* Setup L2 cache */
138144
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
139145
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -189,6 +195,12 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
189195

190196
static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
191197
{
198+
/* These registers are not accessible to VF-SRIOV.
199+
* The PF will program them instead.
200+
*/
201+
if (amdgpu_sriov_vf(adev))
202+
return;
203+
192204
WREG32_SOC15(MMHUB, 0,
193205
mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
194206
0xFFFFFFFF);
@@ -318,6 +330,13 @@ void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
318330
void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
319331
{
320332
u32 tmp;
333+
334+
/* These registers are not accessible to VF-SRIOV.
335+
* The PF will program them instead.
336+
*/
337+
if (amdgpu_sriov_vf(adev))
338+
return;
339+
321340
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
322341
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
323342
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

‎drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -179,12 +179,11 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
179179
}
180180
break;
181181
case CHIP_SIENNA_CICHLID:
182+
case CHIP_NAVY_FLOUNDER:
182183
err = psp_init_ta_microcode(&adev->psp, chip_name);
183184
if (err)
184185
return err;
185186
break;
186-
case CHIP_NAVY_FLOUNDER:
187-
break;
188187
default:
189188
BUG();
190189
}

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2196,6 +2196,7 @@ void amdgpu_dm_update_connector_after_detect(
21962196

21972197
drm_connector_update_edid_property(connector,
21982198
aconnector->edid);
2199+
drm_add_edid_modes(connector, aconnector->edid);
21992200

22002201
if (aconnector->dc_link->aux_mode)
22012202
drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,

‎drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1108,6 +1108,18 @@ static enum bp_result bios_parser_enable_disp_power_gating(
11081108
action);
11091109
}
11101110

1111+
static enum bp_result bios_parser_enable_lvtma_control(
1112+
struct dc_bios *dcb,
1113+
uint8_t uc_pwr_on)
1114+
{
1115+
struct bios_parser *bp = BP_FROM_DCB(dcb);
1116+
1117+
if (!bp->cmd_tbl.enable_lvtma_control)
1118+
return BP_RESULT_FAILURE;
1119+
1120+
return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on);
1121+
}
1122+
11111123
static bool bios_parser_is_accelerated_mode(
11121124
struct dc_bios *dcb)
11131125
{
@@ -2208,7 +2220,9 @@ static const struct dc_vbios_funcs vbios_funcs = {
22082220
.get_board_layout_info = bios_get_board_layout_info,
22092221
.pack_data_tables = bios_parser_pack_data_tables,
22102222

2211-
.get_atom_dc_golden_table = bios_get_atom_dc_golden_table
2223+
.get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
2224+
2225+
.enable_lvtma_control = bios_parser_enable_lvtma_control
22122226
};
22132227

22142228
static bool bios_parser2_construct(

‎drivers/gpu/drm/amd/display/dc/bios/command_table2.c

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -904,6 +904,33 @@ static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)
904904
return 0;
905905
}
906906

907+
/******************************************************************************
908+
******************************************************************************
909+
**
910+
** LVTMA CONTROL
911+
**
912+
******************************************************************************
913+
*****************************************************************************/
914+
915+
static enum bp_result enable_lvtma_control(
916+
struct bios_parser *bp,
917+
uint8_t uc_pwr_on);
918+
919+
static void init_enable_lvtma_control(struct bios_parser *bp)
920+
{
921+
/* TODO add switch for table vrsion */
922+
bp->cmd_tbl.enable_lvtma_control = enable_lvtma_control;
923+
924+
}
925+
926+
static enum bp_result enable_lvtma_control(
927+
struct bios_parser *bp,
928+
uint8_t uc_pwr_on)
929+
{
930+
enum bp_result result = BP_RESULT_FAILURE;
931+
return result;
932+
}
933+
907934
void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
908935
{
909936
init_dig_encoder_control(bp);
@@ -919,4 +946,5 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
919946
init_set_dce_clock(bp);
920947
init_get_smu_clock_info(bp);
921948

949+
init_enable_lvtma_control(bp);
922950
}

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