Skip to content

Commit 43ec1a2

Browse files
konradybciorobclark
authored andcommitted
drm/msm/adreno: De-spaghettify the use of memory barriers
Memory barriers help ensure instruction ordering, NOT time and order of actual write arrival at other observers (e.g. memory-mapped IP). On architectures employing weak memory ordering, the latter can be a giant pain point, and it has been as part of this driver. Moreover, the gpu_/gmu_ accessors already use non-relaxed versions of readl/writel, which include r/w (respectively) barriers. Replace the barriers with a readback (or drop altogether where possible) that ensures the previous writes have exited the write buffer (as the CPU must flush the write to the register it's trying to read back). Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/600869/ Reviewed-by: Akhil P Oommen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
1 parent 1e210f4 commit 43ec1a2

File tree

2 files changed

+7
-7
lines changed

2 files changed

+7
-7
lines changed

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -466,9 +466,7 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
466466
int ret;
467467
u32 val;
468468

469-
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
470-
/* Wait for the register to finish posting */
471-
wmb();
469+
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1));
472470

473471
ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
474472
val & (1 << 1), 100, 10000);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -855,14 +855,16 @@ static int hw_init(struct msm_gpu *gpu)
855855
/* Clear GBIF halt in case GX domain was not collapsed */
856856
if (adreno_is_a619_holi(adreno_gpu)) {
857857
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
858+
gpu_read(gpu, REG_A6XX_GBIF_HALT);
859+
858860
gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0);
859-
/* Let's make extra sure that the GPU can access the memory.. */
860-
mb();
861+
gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL);
861862
} else if (a6xx_has_gbif(adreno_gpu)) {
862863
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
864+
gpu_read(gpu, REG_A6XX_GBIF_HALT);
865+
863866
gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
864-
/* Let's make extra sure that the GPU can access the memory.. */
865-
mb();
867+
gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT);
866868
}
867869

868870
/* Some GPUs are stubborn and take their sweet time to unhalt GBIF! */

0 commit comments

Comments
 (0)