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Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier: - Conversion of the SiFive PLIC to hierarchical domains - New SiFive GPIO irqchip driver - New Aspeed SCI irqchip driver - New NXP INTMUX irqchip driver - Additional support for the Meson A1 GPIO irqchip - First part of the GICv4.1 support - Assorted fixes
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‎Documentation/devicetree/bindings/gpio/sifive,gpio.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive GPIO controller
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maintainers:
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- Yash Shah <[email protected]>
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- Paul Walmsley <[email protected]>
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properties:
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compatible:
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items:
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- const: sifive,fu540-c000-gpio
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- const: sifive,gpio0
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reg:
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maxItems: 1
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interrupts:
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description:
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interrupt mapping one per GPIO. Maximum 16 GPIOs.
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minItems: 1
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maxItems: 16
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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clocks:
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maxItems: 1
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"#gpio-cells":
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const: 2
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gpio-controller: true
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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- clocks
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- "#gpio-cells"
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- gpio-controller
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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gpio@10060000 {
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compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
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interrupt-parent = <&plic>;
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interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
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reg = <0x0 0x10060000 0x0 0x1000>;
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clocks = <&tlclk PRCI_CLK_TLCLK>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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...

‎Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

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"amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
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"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
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"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
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"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- #interrupt-cells : Specifies the number of cells needed to encode an

‎Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt

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Aspeed AST25XX and AST26XX SCU Interrupt Controller
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Required Properties:
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- #interrupt-cells : must be 1
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- compatible : must be "aspeed,ast2500-scu-ic",
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"aspeed,ast2600-scu-ic0" or
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"aspeed,ast2600-scu-ic1"
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- interrupts : interrupt from the parent controller
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- interrupt-controller : indicates that the controller receives and
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fires new interrupts for child busses
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Example:
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syscon@1e6e2000 {
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ranges = <0 0x1e6e2000 0x1a8>;
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scu_ic: interrupt-controller@18 {
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#interrupt-cells = <1>;
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compatible = "aspeed,ast2500-scu-ic";
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interrupts = <21>;
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interrupt-controller;
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};
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};

‎Documentation/devicetree/bindings/interrupt-controller/fsl,intmux.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale INTMUX interrupt multiplexer
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maintainers:
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- Joakim Zhang <[email protected]>
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properties:
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compatible:
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const: fsl,imx-intmux
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 8
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description: |
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Should contain the parent interrupt lines (up to 8) used to multiplex
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the input interrupts.
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description: |
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The 1st cell is hw interrupt number, the 2nd cell is channel index.
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clocks:
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description: ipg clock.
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clock-names:
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const: ipg
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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interrupt-controller@37400000 {
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compatible = "fsl,imx-intmux";
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reg = <0x37400000 0x1000>;
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interrupts = <0 16 4>,
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<0 17 4>,
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<0 18 4>,
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<0 19 4>,
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<0 20 4>,
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<0 21 4>,
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<0 22 4>,
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<0 23 4>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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clocks = <&clk>;
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clock-names = "ipg";
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};

‎MAINTAINERS

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F: drivers/pinctrl/aspeed/
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F: Documentation/devicetree/bindings/pinctrl/aspeed,*
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ASPEED SCU INTERRUPT CONTROLLER DRIVER
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M: Eddie James <[email protected]>
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt
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F: drivers/irqchip/irq-aspeed-scu-ic.c
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F: include/dt-bindings/interrupt-controller/aspeed-scu-ic.h
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ASPEED VIDEO ENGINE DRIVER
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M: Eddie James <[email protected]>
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L: [email protected]

‎arch/arm/include/asm/arch_gicv3.h

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#ifndef __ASSEMBLY__
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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/*
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* GITS_VPROPBASER - hi and lo bits may be accessed independently.
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*/
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#define gits_read_vpropbaser(c) __gic_readq_nonatomic(c)
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#define gits_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)
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/*

‎arch/arm/mach-exynos/Kconfig

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select ARCH_SUPPORTS_BIG_ENDIAN
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select ARM_AMBA
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select ARM_GIC
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select EXYNOS_IRQ_COMBINER
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select COMMON_CLK_SAMSUNG
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select EXYNOS_ASV
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select EXYNOS_CHIPID

‎arch/arm64/include/asm/arch_gicv3.h

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#define gicr_read_pendbaser(c) readq_relaxed(c)
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#define gits_write_vpropbaser(v, c) writeq_relaxed(v, c)
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#define gits_read_vpropbaser(c) readq_relaxed(c)
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#define gits_write_vpendbaser(v, c) writeq_relaxed(v, c)
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#define gits_read_vpendbaser(c) readq_relaxed(c)

‎drivers/gpio/Kconfig

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The difference from regular GPIOs is that they
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maintain their value during backup/self-refresh.
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config GPIO_SIFIVE
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bool "SiFive GPIO support"
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depends on OF_GPIO && IRQ_DOMAIN_HIERARCHY
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select GPIO_GENERIC
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select GPIOLIB_IRQCHIP
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select REGMAP_MMIO
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help
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Say yes here to support the GPIO device on SiFive SoCs.
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config GPIO_SIOX
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tristate "SIOX GPIO support"
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depends on SIOX

‎drivers/gpio/Makefile

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obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o
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obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
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obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
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obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o
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obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o
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obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
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obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o

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