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#define VC5_GLOBAL_REGISTER 0x76
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#define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
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- /* PLL/ VCO runs between 2.5 GHz and 3.0 GHz */
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+ /* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */
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#define VC5_PLL_VCO_MIN 2500000000UL
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- #define VC5_PLL_VCO_MAX 3000000000UL
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/* VC5 Input mux settings */
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#define VC5_MUX_IN_XIN BIT(0)
@@ -150,6 +149,7 @@ enum vc5_model {
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IDT_VC5_5P49V5925 ,
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IDT_VC5_5P49V5933 ,
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IDT_VC5_5P49V5935 ,
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+ IDT_VC6_5P49V60 ,
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IDT_VC6_5P49V6901 ,
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IDT_VC6_5P49V6965 ,
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IDT_VC6_5P49V6975 ,
@@ -161,6 +161,7 @@ struct vc5_chip_info {
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const unsigned int clk_fod_cnt ;
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const unsigned int clk_out_cnt ;
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const u32 flags ;
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+ const unsigned long vco_max ;
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};
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struct vc5_driver_data ;
@@ -446,10 +447,11 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long * parent_rate )
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{
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struct vc5_hw_data * hwdata = container_of (hw , struct vc5_hw_data , hw );
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+ struct vc5_driver_data * vc5 = hwdata -> vc5 ;
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u32 div_int ;
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u64 div_frc ;
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- rate = clamp (rate , VC5_PLL_VCO_MIN , VC5_PLL_VCO_MAX );
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+ rate = clamp (rate , VC5_PLL_VCO_MIN , vc5 -> chip_info -> vco_max );
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/* Determine integer part, which is 12 bit wide */
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div_int = rate / * parent_rate ;
@@ -1209,55 +1211,71 @@ static const struct vc5_chip_info idt_5p49v5923_info = {
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.clk_fod_cnt = 2 ,
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.clk_out_cnt = 3 ,
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.flags = 0 ,
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+ .vco_max = 3000000000UL ,
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};
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static const struct vc5_chip_info idt_5p49v5925_info = {
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.model = IDT_VC5_5P49V5925 ,
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.clk_fod_cnt = 4 ,
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.clk_out_cnt = 5 ,
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.flags = 0 ,
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+ .vco_max = 3000000000UL ,
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};
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static const struct vc5_chip_info idt_5p49v5933_info = {
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.model = IDT_VC5_5P49V5933 ,
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.clk_fod_cnt = 2 ,
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.clk_out_cnt = 3 ,
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.flags = VC5_HAS_INTERNAL_XTAL ,
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+ .vco_max = 3000000000UL ,
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};
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static const struct vc5_chip_info idt_5p49v5935_info = {
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.model = IDT_VC5_5P49V5935 ,
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.clk_fod_cnt = 4 ,
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.clk_out_cnt = 5 ,
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.flags = VC5_HAS_INTERNAL_XTAL ,
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+ .vco_max = 3000000000UL ,
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+ };
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+
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+ static const struct vc5_chip_info idt_5p49v60_info = {
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+ .model = IDT_VC6_5P49V60 ,
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+ .clk_fod_cnt = 4 ,
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+ .clk_out_cnt = 5 ,
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+ .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT ,
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+ .vco_max = 2700000000UL ,
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};
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static const struct vc5_chip_info idt_5p49v6901_info = {
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.model = IDT_VC6_5P49V6901 ,
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.clk_fod_cnt = 4 ,
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.clk_out_cnt = 5 ,
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.flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT ,
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+ .vco_max = 3000000000UL ,
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};
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static const struct vc5_chip_info idt_5p49v6965_info = {
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.model = IDT_VC6_5P49V6965 ,
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.clk_fod_cnt = 4 ,
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.clk_out_cnt = 5 ,
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.flags = VC5_HAS_BYPASS_SYNC_BIT ,
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+ .vco_max = 3000000000UL ,
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};
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static const struct vc5_chip_info idt_5p49v6975_info = {
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.model = IDT_VC6_5P49V6975 ,
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.clk_fod_cnt = 4 ,
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.clk_out_cnt = 5 ,
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.flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL ,
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+ .vco_max = 3000000000UL ,
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};
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static const struct i2c_device_id vc5_id [] = {
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{ "5p49v5923" , .driver_data = IDT_VC5_5P49V5923 },
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{ "5p49v5925" , .driver_data = IDT_VC5_5P49V5925 },
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{ "5p49v5933" , .driver_data = IDT_VC5_5P49V5933 },
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{ "5p49v5935" , .driver_data = IDT_VC5_5P49V5935 },
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+ { "5p49v60" , .driver_data = IDT_VC6_5P49V60 },
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{ "5p49v6901" , .driver_data = IDT_VC6_5P49V6901 },
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{ "5p49v6965" , .driver_data = IDT_VC6_5P49V6965 },
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{ "5p49v6975" , .driver_data = IDT_VC6_5P49V6975 },
@@ -1270,6 +1288,7 @@ static const struct of_device_id clk_vc5_of_match[] = {
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{ .compatible = "idt,5p49v5925" , .data = & idt_5p49v5925_info },
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{ .compatible = "idt,5p49v5933" , .data = & idt_5p49v5933_info },
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{ .compatible = "idt,5p49v5935" , .data = & idt_5p49v5935_info },
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+ { .compatible = "idt,5p49v60" , .data = & idt_5p49v60_info },
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{ .compatible = "idt,5p49v6901" , .data = & idt_5p49v6901_info },
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{ .compatible = "idt,5p49v6965" , .data = & idt_5p49v6965_info },
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{ .compatible = "idt,5p49v6975" , .data = & idt_5p49v6975_info },
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