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ssuthiku-amdjoergroedel
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iommu/amd: Introduce iommu_v1_iova_to_phys
This implements iova_to_phys for AMD IOMMU v1 pagetable, which will be used by the IO page table framework. Signed-off-by: Suravee Suthikulpanit <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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2 files changed

+23
-15
lines changed

2 files changed

+23
-15
lines changed

drivers/iommu/amd/io_pgtable.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -488,6 +488,26 @@ unsigned long iommu_unmap_page(struct protection_domain *dom,
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return unmapped;
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}
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static phys_addr_t iommu_v1_iova_to_phys(struct io_pgtable_ops *ops, unsigned long iova)
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{
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struct amd_io_pgtable *pgtable = io_pgtable_ops_to_data(ops);
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unsigned long offset_mask, pte_pgsize;
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u64 *pte, __pte;
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if (pgtable->mode == PAGE_MODE_NONE)
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return iova;
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pte = fetch_pte(pgtable, iova, &pte_pgsize);
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if (!pte || !IOMMU_PTE_PRESENT(*pte))
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return 0;
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offset_mask = pte_pgsize - 1;
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__pte = __sme_clr(*pte & PM_ADDR_MASK);
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return (__pte & ~offset_mask) | (iova & offset_mask);
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}
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/*
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* ----------------------------------------------------
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*/
@@ -528,6 +548,8 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *coo
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cfg->oas = IOMMU_OUT_ADDR_BIT_SIZE,
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cfg->tlb = &v1_flush_ops;
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pgtable->iop.ops.iova_to_phys = iommu_v1_iova_to_phys;
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return &pgtable->iop;
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}
533555

drivers/iommu/amd/iommu.c

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -2100,22 +2100,8 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
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{
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struct protection_domain *domain = to_pdomain(dom);
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struct io_pgtable_ops *ops = &domain->iop.iop.ops;
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struct amd_io_pgtable *pgtable = io_pgtable_ops_to_data(ops);
2104-
unsigned long offset_mask, pte_pgsize;
2105-
u64 *pte, __pte;
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2107-
if (domain->iop.mode == PAGE_MODE_NONE)
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return iova;
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pte = fetch_pte(pgtable, iova, &pte_pgsize);
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if (!pte || !IOMMU_PTE_PRESENT(*pte))
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return 0;
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offset_mask = pte_pgsize - 1;
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__pte = __sme_clr(*pte & PM_ADDR_MASK);
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return (__pte & ~offset_mask) | (iova & offset_mask);
2104+
return ops->iova_to_phys(ops, iova);
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}
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static bool amd_iommu_capable(enum iommu_cap cap)

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