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Merge tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull Devicetree updates from Rob Herring: - Improve device links cycle detection and breaking. Add more bindings for device link dependencies. - Refactor parsing 'no-map' in __reserved_mem_alloc_size() - Improve DT unittest 'ranges' and 'dma-ranges' test case to check differing cell sizes - Various http to https link conversions - Add a schema check to prevent 'syscon' from being used by itself without a more specific compatible - A bunch more DT binding conversions to schema * tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits) of: reserved-memory: remove duplicated call to of_get_flat_dt_prop() for no-map node of: unittest: Use bigger address cells to catch parser regressions dt-bindings: memory-controllers: Convert mmdc to json-schema dt-bindings: mtd: Convert imx nand to json-schema dt-bindings: mtd: Convert gpmi nand to json-schema dt-bindings: iio: io-channel-mux: Fix compatible string in example code of: property: Add device link support for pinctrl-0 through pinctrl-8 of: property: Add device link support for multiple DT bindings dt-bindings: phy: ti: phy-gmii-sel: convert bindings to json-schema dt-bindings: mux: mux.h: drop a duplicated word dt-bindings: misc: Convert olpc,xo1.75-ec to json-schema dt-bindings: aspeed-lpc: Replace HTTP links with HTTPS ones dt-bindings: drm/bridge: Replace HTTP links with HTTPS ones drm/tilcdc: Replace HTTP links with HTTPS ones dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support dt-bindings: fpga: Replace HTTP links with HTTPS ones dt-bindings: virtio: Replace HTTP links with HTTPS ones dt-bindings: media: imx274: Add optional input clock and supplies dt-bindings: i2c-gpio: Use 'deprecated' keyword on deprecated properties dt-bindings: interrupt-controller: Fix typos in loongson,liointc.yaml ...
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‎Documentation/devicetree/bindings/clock/imx35-clock.yaml

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#clock-cells = <1>;
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};
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esdhc@53fb4000 {
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mmc@53fb4000 {
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compatible = "fsl,imx35-esdhc";
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reg = <0x53fb4000 0x4000>;
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interrupts = <7>;

‎Documentation/devicetree/bindings/clock/imx7ulp-clock.txt

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This file was deleted.

‎Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
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maintainers:
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- A.s. Dong <[email protected]>
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description: |
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i.MX7ULP Clock functions are under joint control of the System
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Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
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modules, and Core Mode Controller (CMC)1 blocks
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The clocking scheme provides clear separation between M4 domain
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and A7 domain. Except for a few clock sources shared between two
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domains, such as the System Oscillator clock, the Slow IRC (SIRC),
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and and the Fast IRC clock (FIRCLK), clock sources and clock
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management are separated and contained within each domain.
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M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
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A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
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Note: this binding doc is only for A7 clock domain.
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The Peripheral Clock Control (PCC) is responsible for clock selection,
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optional division and clock gating mode for peripherals in their
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respected power domain.
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
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i.MX7ULP clock IDs of each module.
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properties:
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compatible:
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enum:
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- fsl,imx7ulp-pcc2
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- fsl,imx7ulp-pcc3
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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items:
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- description: nic1 bus clock
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- description: nic1 clock
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- description: ddr clock
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- description: apll pfd2
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- description: apll pfd1
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- description: apll pfd0
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- description: usb pll
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- description: system osc bus clock
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- description: fast internal reference clock bus
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- description: rtc osc
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- description: system pll bus clock
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clock-names:
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items:
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- const: nic1_bus_clk
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- const: nic1_clk
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- const: ddr_clk
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- const: apll_pfd2
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- const: apll_pfd1
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- const: apll_pfd0
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- const: upll
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- const: sosc_bus_clk
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- const: firc_bus_clk
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- const: rosc
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- const: spll_bus_clk
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx7ulp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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clock-controller@403f0000 {
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compatible = "fsl,imx7ulp-pcc2";
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reg = <0x403f0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&scg1 IMX7ULP_CLK_DDR_DIV>,
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<&scg1 IMX7ULP_CLK_APLL_PFD2>,
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<&scg1 IMX7ULP_CLK_APLL_PFD1>,
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<&scg1 IMX7ULP_CLK_APLL_PFD0>,
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<&scg1 IMX7ULP_CLK_UPLL>,
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<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_ROSC>,
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<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
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clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
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"apll_pfd2", "apll_pfd1", "apll_pfd0",
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"upll", "sosc_bus_clk", "firc_bus_clk",
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"rosc", "spll_bus_clk";
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};
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mmc@40380000 {
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compatible = "fsl,imx7ulp-usdhc";
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reg = <0x40380000 0x10000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&pcc2 IMX7ULP_CLK_USDHC1>;
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clock-names ="ipg", "ahb", "per";
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bus-width = <4>;
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};

‎Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
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maintainers:
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- A.s. Dong <[email protected]>
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description: |
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i.MX7ULP Clock functions are under joint control of the System
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Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
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modules, and Core Mode Controller (CMC)1 blocks
16+
17+
The clocking scheme provides clear separation between M4 domain
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and A7 domain. Except for a few clock sources shared between two
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domains, such as the System Oscillator clock, the Slow IRC (SIRC),
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and and the Fast IRC clock (FIRCLK), clock sources and clock
21+
management are separated and contained within each domain.
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M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
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A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
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Note: this binding doc is only for A7 clock domain.
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The System Clock Generation (SCG) is responsible for clock generation
29+
and distribution across this device. Functions performed by the SCG
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include: clock reference selection, generation of clock used to derive
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processor, system, peripheral bus and external memory interface clocks,
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source selection for peripheral clocks and control of power saving
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clock gating mode.
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The clock consumer should specify the desired clock by having the clock
36+
ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
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i.MX7ULP clock IDs of each module.
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properties:
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compatible:
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const: fsl,imx7ulp-scg1
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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items:
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- description: rtc osc
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- description: system osc
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- description: slow internal reference clock
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- description: fast internal reference clock
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- description: usb PLL
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clock-names:
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items:
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- const: rosc
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- const: sosc
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- const: sirc
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- const: firc
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- const: upll
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx7ulp-clock.h>
78+
#include <dt-bindings/interrupt-controller/arm-gic.h>
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clock-controller@403e0000 {
81+
compatible = "fsl,imx7ulp-scg1";
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reg = <0x403e0000 0x10000>;
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clocks = <&rosc>, <&sosc>, <&sirc>,
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<&firc>, <&upll>;
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clock-names = "rosc", "sosc", "sirc",
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"firc", "upll";
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#clock-cells = <1>;
88+
};
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mmc@40380000 {
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compatible = "fsl,imx7ulp-usdhc";
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reg = <0x40380000 0x10000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&pcc2 IMX7ULP_CLK_USDHC1>;
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clock-names ="ipg", "ahb", "per";
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bus-width = <4>;
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};

‎Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml

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};
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mmc@5b010000 {
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
65+
compatible = "fsl,imx8qxp-usdhc";
6666
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b010000 0x10000>;
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clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,

‎Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt

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--------------------------------
33

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This is the binding for Texas Instruments SN65DSI86 bridge.
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http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
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https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
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Required properties:
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- compatible: Must be "ti,sn65dsi86"

‎Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt

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crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
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for Blue[3-7]. For more details see section 3.1.1 in AM335x
4848
Silicon Errata:
49-
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
49+
https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
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Example:
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‎Documentation/devicetree/bindings/fpga/fpga-region.txt

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--
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[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
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[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
496-
[3] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
496+
[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf

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