@@ -538,10 +538,12 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
538
538
vgic_mmio_read_group , vgic_mmio_write_group , NULL , NULL , 1 ,
539
539
VGIC_ACCESS_32bit ),
540
540
REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED (GICD_ISENABLER ,
541
- vgic_mmio_read_enable , vgic_mmio_write_senable , NULL , NULL , 1 ,
541
+ vgic_mmio_read_enable , vgic_mmio_write_senable ,
542
+ NULL , vgic_uaccess_write_senable , 1 ,
542
543
VGIC_ACCESS_32bit ),
543
544
REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED (GICD_ICENABLER ,
544
- vgic_mmio_read_enable , vgic_mmio_write_cenable , NULL , NULL , 1 ,
545
+ vgic_mmio_read_enable , vgic_mmio_write_cenable ,
546
+ NULL , vgic_uaccess_write_cenable , 1 ,
545
547
VGIC_ACCESS_32bit ),
546
548
REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED (GICD_ISPENDR ,
547
549
vgic_mmio_read_pending , vgic_mmio_write_spending ,
@@ -553,11 +555,11 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
553
555
VGIC_ACCESS_32bit ),
554
556
REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED (GICD_ISACTIVER ,
555
557
vgic_mmio_read_active , vgic_mmio_write_sactive ,
556
- NULL , vgic_mmio_uaccess_write_sactive , 1 ,
558
+ vgic_uaccess_read_active , vgic_mmio_uaccess_write_sactive , 1 ,
557
559
VGIC_ACCESS_32bit ),
558
560
REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED (GICD_ICACTIVER ,
559
561
vgic_mmio_read_active , vgic_mmio_write_cactive ,
560
- NULL , vgic_mmio_uaccess_write_cactive ,
562
+ vgic_uaccess_read_active , vgic_mmio_uaccess_write_cactive ,
561
563
1 , VGIC_ACCESS_32bit ),
562
564
REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED (GICD_IPRIORITYR ,
563
565
vgic_mmio_read_priority , vgic_mmio_write_priority , NULL , NULL ,
@@ -609,11 +611,13 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = {
609
611
REGISTER_DESC_WITH_LENGTH (SZ_64K + GICR_IGROUPR0 ,
610
612
vgic_mmio_read_group , vgic_mmio_write_group , 4 ,
611
613
VGIC_ACCESS_32bit ),
612
- REGISTER_DESC_WITH_LENGTH (SZ_64K + GICR_ISENABLER0 ,
613
- vgic_mmio_read_enable , vgic_mmio_write_senable , 4 ,
614
+ REGISTER_DESC_WITH_LENGTH_UACCESS (SZ_64K + GICR_ISENABLER0 ,
615
+ vgic_mmio_read_enable , vgic_mmio_write_senable ,
616
+ NULL , vgic_uaccess_write_senable , 4 ,
614
617
VGIC_ACCESS_32bit ),
615
- REGISTER_DESC_WITH_LENGTH (SZ_64K + GICR_ICENABLER0 ,
616
- vgic_mmio_read_enable , vgic_mmio_write_cenable , 4 ,
618
+ REGISTER_DESC_WITH_LENGTH_UACCESS (SZ_64K + GICR_ICENABLER0 ,
619
+ vgic_mmio_read_enable , vgic_mmio_write_cenable ,
620
+ NULL , vgic_uaccess_write_cenable , 4 ,
617
621
VGIC_ACCESS_32bit ),
618
622
REGISTER_DESC_WITH_LENGTH_UACCESS (SZ_64K + GICR_ISPENDR0 ,
619
623
vgic_mmio_read_pending , vgic_mmio_write_spending ,
@@ -625,12 +629,12 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = {
625
629
VGIC_ACCESS_32bit ),
626
630
REGISTER_DESC_WITH_LENGTH_UACCESS (SZ_64K + GICR_ISACTIVER0 ,
627
631
vgic_mmio_read_active , vgic_mmio_write_sactive ,
628
- NULL , vgic_mmio_uaccess_write_sactive ,
629
- 4 , VGIC_ACCESS_32bit ),
632
+ vgic_uaccess_read_active , vgic_mmio_uaccess_write_sactive , 4 ,
633
+ VGIC_ACCESS_32bit ),
630
634
REGISTER_DESC_WITH_LENGTH_UACCESS (SZ_64K + GICR_ICACTIVER0 ,
631
635
vgic_mmio_read_active , vgic_mmio_write_cactive ,
632
- NULL , vgic_mmio_uaccess_write_cactive ,
633
- 4 , VGIC_ACCESS_32bit ),
636
+ vgic_uaccess_read_active , vgic_mmio_uaccess_write_cactive , 4 ,
637
+ VGIC_ACCESS_32bit ),
634
638
REGISTER_DESC_WITH_LENGTH (SZ_64K + GICR_IPRIORITYR0 ,
635
639
vgic_mmio_read_priority , vgic_mmio_write_priority , 32 ,
636
640
VGIC_ACCESS_32bit | VGIC_ACCESS_8bit ),
0 commit comments